Fine Pitch Wirebonds on Ultra Low-k Device

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The mechanical integrity of wirebonds are sensitive to structures under the bond pads of ultra low-k dielectric devices. The authors studied the mechanical performance of wirebonds on 32-nm test chips with various layouts of lines and vias under the 35-μm-pitch bond pads, various stacks of dielectric layers, and a range of bonding process conditions. Poor mechanical integrity resulted in the pad tearout failure mode at wire pull testing. The thickness of the SiO2/FTEOS layer and the density of the vias in the ULK layer are the key factors for good wirebond integrity, manufacturability, and module-level reliability with ultrafine pitch wirebonds. The wirebond experimental results were analyzed by capillary indentation, excessive bond force parameter and finite element method (FEM). The authors found that only excessive bond force does not increase the rate of pad tearout and 2D FEM model can correlate the location of pad tearout in the ULK layers with calculated highest stress point which occurs by the ultrasonic vibration during wirebonding process.

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