Bypass Extended Stack Processing for Anti-Thrashing Replacement in Shared Last Level Cache of Chip Multiprocessors

• EOM Young-Sik

  School of EECS, Seoul National University

• KWAK Jong Wook

  Department of Computer Engineering, Yeungnam University

• JHANG Seong-Tae

  Department of Computer Science, The University of Suwon

• JHON Chu-Shik

  School of EECS, Seoul National University

抄録

Chip Multiprocessors (CMPs) allow different applications to share LLC (Last Level Cache). Since each application has different cache capacity demand, LLC capacity should be partitioned in accordance with the demands. Existing partitioning algorithms estimate the capacity demand of each core by stack processing considering the LRU (Least Recently Used) replacement policy only. However, anti-thrashing replacement algorithms like BIP (Binary Insertion Policy) and BIP-Bypass emerged to overcome the thrashing problem of LRU replacement policy in a working set greater than the available cache size. Since existing stack processing cannot estimate the capacity demand with anti-thrashing replacement policy, partitioning algorithms also cannot partition cache space with anti-thrashing replacement policy. In this letter, we prove that BIP replacement policy is not feasible to stack processing but BIP-bypass is. We modify stack processing to accommodate BIP-Bypass. In addition, we propose the pipelined hardware of modified stack processing. With this hardware, we can get the success function of the various capacities with anti-thrashing replacement policy and assess the cache capacity of shared cache adequate to each core in real time.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E96.D (2), 370-374, 2013

  一般社団法人 電子情報通信学会

キーワード

• last level cache
• stack processing
• replacement policy
• anti-thrashing
• cache partitioning
• chip multi-processors

詳細情報

• CRID: 1390282679353989120
• NII論文ID: 10031167417
• NII書誌ID: AA10826272
• DOI: 10.1587/transinf.e96.d.370
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E96.D/2/E96.D_370/_pdf
• 本文言語コード: en
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