A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures
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- Hagio Yuta
- Department of Computer Science and Engineering, Waseda University
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- Yanagisawa Masao
- Department of Electronic and Photonic Systems, Waseda University
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- Togawa Nozomu
- Department of Computer Science and Engineering, Waseda University
抄録
As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
収録刊行物
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- Information and Media Technologies
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Information and Media Technologies 9 (4), 446-455, 2014
Information and Media Technologies 編集運営会議
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詳細情報 詳細情報について
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- CRID
- 1390001205265700992
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- NII論文ID
- 130004705279
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- ISSN
- 18810896
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可