Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC

• ZHAO Wenjun

  Department of Information Systems Engineering, School of Information Science and Technology, Osaka University

• ONOYE Takao

  Department of Information Systems Engineering, School of Information Science and Technology, Osaka University

• SONG Tian

  Department of Electrical and Electronic Engineering, School of Engineering, Tokushima University

抄録

In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A (8), 1787-1795, 2015

  一般社団法人 電子情報通信学会

キーワード

• fast mode decision
• H.265/HEVC
• hardware architecture
• mode dispatch module

詳細情報

• CRID: 1390282681286803840
• NII論文ID: 130005089906
• DOI: 10.1587/transfun.e98.a.1787
• ISSN: 17451337
• ISSN: 09168508
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E98.A/8/E98.A_1787/_pdf
• 本文言語コード: en
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