Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

• Zhang Ran

  Graduate School of Information, Production and Systems, Waseda University

• Pan Tieyuan

  Graduate School of Information, Production and Systems, Waseda University

• Zhu Li

  Graduate School of Information, Production and Systems, Waseda University

• Watanabe Takahiro

  Graduate School of Information, Production and Systems, Waseda University

抄録

In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.

収録刊行物

• IPSJ Transactions on System LSI Design Methodology

  IPSJ Transactions on System LSI Design Methodology 8 (0), 75-84, 2015

  一般社団法人 情報処理学会

キーワード

• PCB routing
• equal-length routing
• single commodity flow
• EDA

詳細情報

• CRID: 1390001205291999104
• NII論文ID: 130005091211
• DOI: 10.2197/ipsjtsldm.8.75
• ISSN: 18826687
• Web Site: https://www.jstage.jst.go.jp/article/ipsjtsldm/8/0/8_75/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可