A CMOS circuit for PWM-mode nonlinear transformation robust to device mismatches to implement coupled map lattice models

DOI Web Site 被引用文献2件 参考文献10件 オープンアクセス
  • Uenohara Seiji
    Graduate School of Life Science and Systems, Kyushu Institute of Technology
  • Atuti Daisuke
    Graduate School of Life Science and Systems, Kyushu Institute of Technology
  • Matsuzaka Kenji
    Graduate School of Life Science and Systems, Kyushu Institute of Technology
  • Tamukoh Hakaru
    Graduate School of Life Science and Systems, Kyushu Institute of Technology
  • Morie Takashi
    Graduate School of Life Science and Systems, Kyushu Institute of Technology
  • Aihara Kazuyuki
    Institute of Industrial Science, The University of Tokyo

抄録

In order to develop large-scale nonlinear dynamical systems using CMOS integrated circuits, we propose a core circuit for coupled map lattice (CML) models. The characteristics of the core circuits in the lattice on a chip are not generally equal, which is caused by CMOS device mismatches, including parasitic capacitance and wiring resistance. The proposed circuit solves this problem; it compensates for a DC offset voltage variation by holding it at a capacitor, and also for current variation by adjusting the bias voltage of a current source automatically so as to bring the current close to a target value. The proposed core circuit has been designed and fabricated using TSMC 0.25 µm CMOS technology. The measurement results using the fabricated circuit have shown that the bit precision is more than 8 bits, even if there is a DC offset voltage of 100 mV or a bias-voltage change of 100 mV in a switched current source.

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