A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists
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- OYA Masaru
- Dept. of Computer Science and Communication Engineering, Waseda University
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- SHI Youhua
- Waseda Institute for Advanced Study, Waseda University
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- YAMASHITA Noritaka
- Cloud System Research Laboratories, NEC Corporation
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- OKAMURA Toshihiko
- Cloud System Research Laboratories, NEC Corporation
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- TSUNOO Yukiyasu
- Cloud System Research Laboratories, NEC Corporation
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- GOTO Satoshi
- Graduate School of Information, Production and Systems, Waseda University
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- YANAGISAWA Masao
- Dept. of Computer Science and Communication Engineering, Waseda University
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- TOGAWA Nozomu
- Dept. of Computer Science and Communication Engineering, Waseda University
抄録
Outsourcing IC design and fabrication is one of the effective solutions to reduce design cost but it may cause severe security risks. Particularly, malicious outside vendors may implement Hardware Trojans (HTs) on ICs. When we focus on IC design phase, we cannot assume an HT-free netlist or a Golden netlist and it is too difficult to identify whether a given netlist is HT-free or not. In this paper, we propose a score-based hardware-trojans identifying method at gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but it detects a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks and ISCAS85 benchmarks as well as HT-free and HT-inserted AES gate-level netlists. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be “HT-inserted” and all the HT-free gate-level benchmarks to be “HT-free” in approximately three hours for each benchmark.
収録刊行物
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E98.A (12), 2537-2546, 2015
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詳細情報 詳細情報について
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- CRID
- 1390282681289158656
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- NII論文ID
- 130005112009
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- ISSN
- 17451337
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可