A Precise Model for Cross-Point Memory Array

• ASAO Yoshiaki

  Toshiba

• HORIGUCHI Fumio

  Toyo University

抄録

A simplified circuit has been utilized for fast computation of the current flowing in the cross-point memory array. However, the circuit has a constraint in that the selected cell is located farthest from current drivers so as to estimate the current degraded by metal wire resistance. This is because the length of the current path along the metal wire varies with the selected address in the cross-point memory array. In this paper, a new simplified circuit is proposed for calculating the current at every address in order to take account of the metal wire resistance. By employing the Monte Carlo simulation to solve the proposed simplified circuit, the current distribution across the array is obtained, so that failure rates of read disturbance and write error are estimated precisely. By comparing the conventional and the proposed simplified circuits, it was found that the conventional simplified circuit estimated optimistic failure rates for read disturbance and for write error when the wire resistance was prominent enough as a parasitic resistance.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E99.C (1), 119-128, 2016

  一般社団法人 電子情報通信学会

キーワード

• cross-point
• simplified circuit
• Monte Carlo simulation
• read disturbance
• write error

詳細情報

• CRID: 1390282679355464576
• NII論文ID: 130005116157
• DOI: 10.1587/transele.e99.c.119
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E99.C/1/E99.C_119/_pdf
• 本文言語コード: en
• データソース種別:
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  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可