A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

• BAE Jungnam

  Graduate School of Engineering, Osaka University

• RADHAPURAM Saichandrateja

  Graduate School of Engineering, Osaka University

• JO Ikkyun

  Graduate School of Engineering, Osaka University

• WANG Weimin

  Graduate School of Engineering, Osaka University

• KIHARA Takao

  Faculty of Engineering, Osaka Institute of Technology

• MATSUOKA Toshimasa

  Graduate School of Engineering, Osaka University

抄録

A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm², consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E99.C (4), 431-439, 2016

  一般社団法人 電子情報通信学会

キーワード

• all-digital phase-locked loop
• controller
• digitally-controlled oscillator
• phase interpolator
• CMOS
• MICS

詳細情報

• CRID: 1390282679355240832
• NII論文ID: 130005141345
• DOI: 10.1587/transele.e99.c.431
• ISSN: 17451353
• ISSN: 09168524
• HANDLE: 11094/55420
• Web Site: https://www.jstage.jst.go.jp/article/transele/E99.C/4/E99.C_431/_pdf
• 本文言語コード: en
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