A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design
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- IGAWA Koki
- Department of Computer Science and Communications Engineering, Waseda University
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- YANAGISAWA Masao
- Department of Computer Science and Communications Engineering, Waseda University
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- TOGAWA Nozomu
- Department of Computer Science and Communications Engineering, Waseda University
抄録
In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a multi-scenario high-level synthesis algorithm for variation-tolerant floorplan-driven design targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. At that time, we can explicitly take into account interconnection delays by using distributed-register architectures. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.
収録刊行物
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E99.A (7), 1278-1293, 2016
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詳細情報 詳細情報について
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- CRID
- 1390282681287644160
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- NII論文ID
- 130005159589
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- ISSN
- 17451337
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- JaLC
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