Analytical inverter chain’s delay and its variation model for sub-threshold circuits
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- Guo Jingjing
- National ASIC System Engineering Technology Research Center, Southeast University
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- Zhu Jizhe
- National ASIC System Engineering Technology Research Center, Southeast University
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- Wang Min
- National ASIC System Engineering Technology Research Center, Southeast University
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- Nie Jianxin
- National ASIC System Engineering Technology Research Center, Southeast University
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- Liu Xinning
- National ASIC System Engineering Technology Research Center, Southeast University
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- Ge Wei
- National ASIC System Engineering Technology Research Center, Southeast University
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- Yang Jun
- National ASIC System Engineering Technology Research Center, Southeast University
抄録
<p>Sub-threshold circuit is a promising circuit design style for IoT application. This paper concentrated on the delay model based on the transient current model in the sub-threshold region. In order to deduce the path delay model, two ways are adopted, which are the coupling capacitance equivalence and the output waveform equivalence. The distribution of path delays is rigidly proven to be lognormal distribution in the sub-threshold region. Considering different supply voltages, cell driven strengths and load capacitances, the proposed model is also validated by Monte Carlo Spice simulation under SMIC 40 nm CMOS process. Experiments show that proposed model agrees with MC simulation results with error 0.448% under the condition of 0.4 V and 99.7% probability, which proves the feasibility of the model.</p>
収録刊行物
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- IEICE Electronics Express
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IEICE Electronics Express 14 (11), 20170390-20170390, 2017
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390001205219706368
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- NII論文ID
- 130005695900
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- ISSN
- 13492543
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可