Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

    • Kim Seok-Sik
    • Samsung Electronics Co., Ltd., Yongin, Kyounggi-do 446-711, Korea

    • Moon Joo-Tae
    • Samsung Electronics Co., Ltd., Yongin, Kyounggi-do 446-711, Korea
    • Jung Soon-Moon
    • Samsung Electronics Co., Ltd., Yongin, Kyounggi-do 446-711, Korea
    • Son Yong-Hoon
    • Samsung Electronics Co., Ltd., Yongin, Kyounggi-do 446-711, Korea
    • Park Hyunho
    • School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea

    • Jeong Hanwook
    • School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea
    • Kim Kwang-Ryul
    • School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea
    • Choi Byoungdeog
    • School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea

Abstract

Solid phase epitaxy (SPE) techniques have been studied to realize stacked static random memory (SRAM) devices. Among the candidates including epitaxial lateral overgrowth (ELO) and laser epitaxial growth (LEG) techniques, SPE is the most stable and cost-effective scheme since it is fulfilled by the deposition of amorphous silicon layers and the subsequent low temperature annealing using conventional furnace equipment which has been used for several decades in semiconductor fabrication. We introduced silicon seeds for the epitaxial realignment of amorphous silicon within the contact window by the selective epitaxial growth (SEG) of single-crystalline silicon. The role of process variables associated with channel silicon deposition on SPE was investigated. The efficiency of SPE was quantified by electron back-scatter diffraction (EBSD) measurement, which visualizes the fraction of the $\langle 100\rangle$ orientation in a channel silicon layer. SiH4 ambient during the ramp-up stage in the deposition of amorphous silicon layers showed superior epitaxial realignment to N2 ambient, which was mainly due to the suppression of interfacial layer formation. Electrical characteristics such as on-current distribution and static noise margin indicated SPE to be feasible for high-density stacked SRAM application.

Journal

Jpn J Appl Phys  

Jpn J Appl Phys 50(1), 01AB06-01AB06-6, 2011-01-25 

The Japan Society of Applied Physics

Codes

  • NII Article ID (NAID) :
    150000055132
  • NII NACSIS-CAT ID (NCID) :
    AA12295836
  • Text Lang :
    EN
  • Article Type :
    特集
  • Journal Type :
    大学紀要
  • ISSN :
    00214922
  • NDL Article ID :
    10947773
  • NDL Source Classification :
    ZM35(科学技術--物理学)
  • NDL Call No. :
    Z53-A375
  • Databases :
    NDL  JSAP/JPS 

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