Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

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  • D. A. Carl
    Department of Chemical Engineering, University of California, Berkeley, California 94720
  • D. W. Hess
    Department of Chemical Engineering, University of California, Berkeley, California 94720
  • M. A. Lieberman
    Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720
  • T. D. Nguyen
    Center for X-Ray Optics, Lawrence Berkeley Laboratory (LBL), Department of Materials Science and Mineral Engineering, University of California, Berkeley, California 94720
  • R. Gronsky
    National Center for Electron Microscopy, LBL and Department of Materials Science and Mineral Engineering, University of California, Berkeley, California 94720

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<jats:p>Thin (3–300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O−, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5–60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K.</jats:p> <jats:p>High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4–30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm−2) and interface traps (≳1012 cm−2 eV−1). The fixed charge level could be reduced to ≊4×1010 cm−2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1–2)×1011 cm−2 eV−1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm−1. Electrical properties of the 5.4–8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.</jats:p>

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