Stress migration resistance and contact characterization of Al–Pd–Si interconnects for very large scale integrations

DOI PDF 被引用文献3件
  • Y. Koubuchi
    Hitachi Research Laboratory, Hitachi, Ltd. 4026 Kuji, Hitachi, Ibaraki, Japan
  • J. Onuki
    Hitachi Research Laboratory, Hitachi, Ltd. 4026 Kuji, Hitachi, Ibaraki, Japan
  • M. Suwa
    Hitachi Research Laboratory, Hitachi, Ltd. 4026 Kuji, Hitachi, Ibaraki, Japan
  • S. Fukada
    Hitachi Research Laboratory, Hitachi, Ltd. 4026 Kuji, Hitachi, Ibaraki, Japan
  • S. Moribe
    Semiconductor Design and Development Center, Hitachi, Ltd., 5-20-1 Josuihoncho, Kodaira, Tokyo, Japan
  • Y. Tanigaki
    Semiconductor Design and Development Center, Hitachi, Ltd., 5-20-1 Josuihoncho, Kodaira, Tokyo, Japan

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<jats:p>Stress-induced migration resistance and contacts to silicon of Al–0.3%Pd–1%Si interconnections for submicron process integrated circuit devices have been investigated and compared to Al–0.5%Cu–1%Si. Using creep tests, Pd has been found to be an excellent additional element to Al for reducing grain boundary diffusion. Palladium improved the stress-induced migration resistance and reduced void and hillock formation in Al–Si conductors. Aluminum palladium precipitates in Al–Pd–Si alloys were found to be formed at higher temperatures than aluminum copper compounds and may be the reason for the improvements. The contact resistance of Al–Pd–Si was found to be similar to that of Al–Cu–Si. The reliability and yield data from 1.2 μm ROM test devices using Al–Pd–Si conductors is better than that of Al–Cu–Si conductors.</jats:p>

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