任意の精度に被除数を拡張できる並列除算器の提案

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  • A Proposal of Cascadable Parallel Divider on Dividend for Any Word Length
  • ニンイ ノ セイド ニ ヒジョスウ オ カクチョウデキル ヘイレツ ジョザンキ

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The paper proposes a method of digital parallel divider circuit module and its one-chip integration. The multiplication and division are performed very frequently in computers, electronic control systems, signal processing for sound, and image processing. So far, we have proposed a new module of multiplier and divider, which is easily cascadable to perform arithmetic for any word length, without the use of external circuitry. As the multipliers are used more frequently, many fast multipliers with high precision have been proposed and integrated. But there are few one-chip dividers, because they are available only within the limited word length of dividend. So that, there are few merits of making one-chip integrated dividers.<br>The proposed parallel divider circuit module is cascadable on dividend for any word length, without the use of external circuitry. The soundness of the circuit was confirmed by computer simulation.<br>We can design a system without the restriction of the bit length of dividend by using this divider. The proposed method makes it possible to implement one-chip integrated dividers suitable for fast division for any word length.

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