Studies on logic simulation and hardware description languages 論理シミュレーションとハードウェア記述言語に関する研究

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著者

    • 石浦, 菜岐佐 イシウラ, ナギサ

書誌事項

タイトル

Studies on logic simulation and hardware description languages

タイトル別名

論理シミュレーションとハードウェア記述言語に関する研究

著者名

石浦, 菜岐佐

著者別名

イシウラ, ナギサ

学位授与大学

京都大学

取得学位

工学博士

学位授与番号

乙第7496号

学位授与年月日

1991-03-23

注記・抄録

博士論文

目次

  1. 論文目録 / (0001.jp2)
  2. Contents / p7 (0007.jp2)
  3. Abstract / p1 (0004.jp2)
  4. Contents / p7 (0007.jp2)
  5. 1 Introduction / p1 (0010.jp2)
  6. 1.1 Backgrounds / p1 (0010.jp2)
  7. 1.2 Outline of the Thesis / p5 (0012.jp2)
  8. 2 Logic Simulation / p11 (0015.jp2)
  9. 2.1 Modeling of Logic Circuits for Logic Simulation / p11 (0015.jp2)
  10. 2.2 Basic Algorithms for Logic Simulation / p17 (0018.jp2)
  11. 3 Fast Logic Simulation Using Vector Super Computers / p25 (0022.jp2)
  12. 3.1 Introduction / p25 (0022.jp2)
  13. 3.2 Vector Supercomputers / p28 (0024.jp2)
  14. 3.3 Vectorization of Combinational Circuit Simulation. / p32 (0026.jp2)
  15. 3.4 Vectorization of Sequential Circuit Simulation / p48 (0034.jp2)
  16. 3.5 Vectorization of Event-Driven Simulation / p60 (0040.jp2)
  17. 3.6 Remarks and Discussions / p72 (0046.jp2)
  18. 4 Fast Fault Simulation Using Vector Super Computers / p75 (0047.jp2)
  19. 4.1 Introduction / p75 (0047.jp2)
  20. 4.2 Dynamic Two-Dimensional Parallel Simulation Technique / p77 (0048.jp2)
  21. 4.3 Multiple Fault Propagation / p84 (0052.jp2)
  22. 4.4 Implementation and Experiments / p93 (0056.jp2)
  23. 4.5 Remarks and Discussions / p96 (0058.jp2)
  24. 5 Computational Complexity of Logic Simulation Problems / p99 (0059.jp2)
  25. 5.1 Introduction / p99 (0059.jp2)
  26. 5.2 Hazard Detection Problem and Modeling of Delay and Time / p101 (0060.jp2)
  27. 5.3 Hazard Detection Problems of the Discrete Time Model / p105 (0062.jp2)
  28. 5.4 Relation between the Continuous Time Model and the Discrete Time Model / p108 (0064.jp2)
  29. 5.5 Hazard Detection Problems of the Continuous Time Model / p115 (0067.jp2)
  30. 5.6 Remarks and Discussions / p120 (0070.jp2)
  31. 5.A Proof of Lem 5.5 / p122 (0071.jp2)
  32. 6 Time-Symbolic Simulation for Accurate Timing Verification / p125 (0072.jp2)
  33. 6.1 Introduction / p125 (0072.jp2)
  34. 6.2 Problems of Conventional Min/Max Delay Simulation / p128 (0074.jp2)
  35. 6.3 Time-Symbolic Simulation Based on T-Algorithm / p130 (0075.jp2)
  36. 6.4 Timing Verification by Time-Symbolic Simulation / p138 (0079.jp2)
  37. 6.5 Coded Time-Symbolic Simulation-CTSS / p144 (0082.jp2)
  38. 6.6 Timing Verification by Coded Time-Symbolic Simulation / p151 (0085.jp2)
  39. 6.7 Remarks and Discussions / p156 (0088.jp2)
  40. 7 NES:A Nondeterministic Behavior Model for Hardware Description Languages / p159 (0089.jp2)
  41. 7.1 Introduction / p159 (0089.jp2)
  42. 7.2 Basic Concepts of the NES Model / p162 (0091.jp2)
  43. 7.3 Modeling and Description of Behavior of a Hardware Module / p165 (0092.jp2)
  44. 7.4 Modeling and Descriptions of Connected Modules / p172 (0096.jp2)
  45. 7.5 Applications of the NES Model / p175 (0097.jp2)
  46. 7.6 Remarks and Considerations / p178 (0099.jp2)
  47. 8 Conclusions / p181 (0100.jp2)
  48. References / p187 (0103.jp2)
  49. Acknowledgment / p197 (0108.jp2)
  50. List of Publications by the Author / p199 (0109.jp2)
  51. Major Publications / p199 (0109.jp2)
  52. Technical Reports / p202 (0111.jp2)
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各種コード

  • NII論文ID(NAID)
    500000073990
  • NII著者ID(NRID)
    • 8000000074187
  • DOI(NDL)
  • NDL書誌ID
    • 000000238304
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
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