A study of numerical process and device modeling CAD for submicrometer CMOS サブミクロンCMOSプロセス/デバイスに関する数値モデリングに基づいたCADの研究

Access this Article

Search this Article

Author

    • 小田中, 紳二 オダナカ, シンジ

Bibliographic Information

Title

A study of numerical process and device modeling CAD for submicrometer CMOS

Other Title

サブミクロンCMOSプロセス/デバイスに関する数値モデリングに基づいたCADの研究

Author

小田中, 紳二

Author(Another name)

オダナカ, シンジ

University

京都大学

Types of degree

工学博士

Grant ID

乙第7497号

Degree year

1991-03-23

Note and Description

博士論文

Table of Contents

  1. 論文目録 / (0001.jp2)
  2. ABSTRACT / p1 (0006.jp2)
  3. CONTENTS / p3 (0007.jp2)
  4. 1.INTRODUCTION / p1 (0014.jp2)
  5. 1.1 Introduction / p1 (0014.jp2)
  6. 1.2 History of Numerical Silicon Device Modeling / p2 (0015.jp2)
  7. 1.3 History of Numerical Silicon Process Modeling / p4 (0016.jp2)
  8. 1.4 CMOS:The Emerging VLSI Technology / p5 (0016.jp2)
  9. 1.5 Overview / p8 (0018.jp2)
  10. 2.NUMERICAL PROCESS MODELING AND SIMULATION / p11 (0019.jp2)
  11. 2.1 Introduction / p11 (0019.jp2)
  12. 2.2 Ion Implantation Model / p12 (0020.jp2)
  13. 2.3 Diffusion Model / p13 (0020.jp2)
  14. 2.4 Oxidation Model / p19 (0023.jp2)
  15. 2.5 Efficient Numerical Algorithms For Three-Dimensional Process Modeling / p25 (0026.jp2)
  16. 2.6 Applications to LOCOS and Trench Isolation Processes / p32 (0030.jp2)
  17. 2.7 Conclusions / p35 (0031.jp2)
  18. 3.NUMERICAL MOSFET MODELING AND SIMULATION / p36 (0032.jp2)
  19. 3.1 Introduction / p36 (0032.jp2)
  20. 3.2 Set of Semiconductor Device Equations / p37 (0032.jp2)
  21. 3.3 A Three-Dimensional CAD Model for 0.5 μm MOSFET / p41 (0034.jp2)
  22. 3.4 Avalanche Breakdown Simulation of Small Geometry MOSFET / p68 (0048.jp2)
  23. 3.5 Summary / p74 (0051.jp2)
  24. 4.DYNAMICS OF CMOS LATCHUP TURN-ON BEHAVIOR / p75 (0051.jp2)
  25. 4.1 Introduction / p75 (0051.jp2)
  26. 4.2 Transient Model for CMOS Latchup / p76 (0052.jp2)
  27. 4.3 CMOS Structure / p77 (0052.jp2)
  28. 4.4 Surface Induced Latchup Triggering By The Parasitic p-MOSFET / p81 (0054.jp2)
  29. 4.5 Latchup Triggering By Direct Forward Biasing / p86 (0057.jp2)
  30. 4.6 Discussion / p91 (0059.jp2)
  31. 4.7 Summary / p94 (0061.jp2)
  32. 5.A SELF-ALIGNED RETROGRADE TWIN-WELL STRUCTURE WITH BURIED p+₋LAYER / p95 (0061.jp2)
  33. 5.1 Introduction / p95 (0061.jp2)
  34. 5.2 Fabrication Sequence / p96 (0062.jp2)
  35. 5.3 Isolation Characteristics and CMOS latchup Immunity / p103 (0065.jp2)
  36. 5.4 Conclusions / p107 (0067.jp2)
  37. 6.DESIGN OF HALF-MICROMETER p-CHANNEL MOSFET / p108 (0068.jp2)
  38. 6.1 Introduction / p108 (0068.jp2)
  39. 6.2 Scaling Down of Buried p-Channel MOSFETs / p109 (0068.jp2)
  40. 6.3 A New Buried p-Channel MOSFET / p114 (0071.jp2)
  41. 6.4 Device Characteristics / p115 (0071.jp2)
  42. 6.5 Summary / p121 (0074.jp2)
  43. 7.CHARACTERIZATION OF TRENCH ISOLATED p-CHANNEL MOSFET / p123 (0075.jp2)
  44. 7.1 Introduction / p123 (0075.jp2)
  45. 7.2 Trench Isolation Process / p124 (0076.jp2)
  46. 7.3 Experimental Results and Simulations / p126 (0077.jp2)
  47. 7.4 Narrow-Width Effects of Trench Isolated p-Channel MOSFET / p127 (0077.jp2)
  48. 7.5 Conclusions / p131 (0079.jp2)
  49. 8.SUMMARY AND CONCLUSIONS / p133 (0080.jp2)
  50. TECHNICAL PAPERS,INTERNATIONAL CONFERENCE,AND DOMESTIC CONFERENCE / p137 (0082.jp2)
  51. OTHER PAPERS RELATED TO THIS THESIS / p140 (0084.jp2)
  52. REFERENCES / p143 (0085.jp2)
10access

preview

Codes

  • NII Article ID (NAID)
    500000073991
  • NII Author ID (NRID)
    • 8000000074188
  • DOI(NDL)
  • Text Lang
    • eng
  • NDLBibID
    • 000000238305
  • Source
    • Institutional Repository
    • NDL ONLINE
    • NDL Digital Collections

Export

Page Top