Studies on polycrystalline silicon films for high-speed memory LSI's 超高速メモリLSIにおける多結晶シリコン薄膜の研究

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著者

    • 相良, 和彦 サガラ, カズヒコ

書誌事項

タイトル

Studies on polycrystalline silicon films for high-speed memory LSI's

タイトル別名

超高速メモリLSIにおける多結晶シリコン薄膜の研究

著者名

相良, 和彦

著者別名

サガラ, カズヒコ

学位授与大学

慶應義塾大学

取得学位

工学博士

学位授与番号

乙第2323号

学位授与年月日

1991-03-05

注記・抄録

博士論文

目次

  1. 論文目録 / p37 (0001.jp2)
  2. CONTENT / p1 (0005.jp2)
  3. Chapter1.Introduction / p1 (0007.jp2)
  4. 1.1 Motivation / p1 (0007.jp2)
  5. 1.2 Objective and contents of this thesis / p4 (0009.jp2)
  6. References for Chapter1 / p6 (0010.jp2)
  7. Chapter2.Characterization of polycrystalline silicon films / p10 (0012.jp2)
  8. 2.1 Historical backgrounds / p10 (0012.jp2)
  9. 2.2 General properties / p13 (0013.jp2)
  10. 2.3 Technological problems / p20 (0017.jp2)
  11. References for Chapter2 / p22 (0018.jp2)
  12. Chapter3.Effect of grain parameters on electrical properties in polycrystalline silicon films / p29 (0021.jp2)
  13. 3.1 Introduction / p29 (0021.jp2)
  14. 3.2 Experimental procedure / p30 (0022.jp2)
  15. 3.3 Result and discussion / p35 (0024.jp2)
  16. 3.4 Conelusion / p40 (0027.jp2)
  17. References for Chapter3 / p42 (0028.jp2)
  18. Chapter4.Effect of grain structure on the e1ectrical characteristics of polysilicon Schottky Barrier Diodes / p54 (0034.jp2)
  19. 4.1 Introduction / p54 (0034.jp2)
  20. 4.2 Experiment / p55 (0034.jp2)
  21. 4.3 Result and discussion / p56 (0035.jp2)
  22. 4.4 Conclusions / p63 (0038.jp2)
  23. References for Chapter4 / p65 (0039.jp2)
  24. Chapter5.Effect of Poly-Si/Si Interfacial Oxides on Impurity Diffusion Process / p72 (0043.jp2)
  25. 5.1 Introduction / p72 (0043.jp2)
  26. 5.2 Experimental / p73 (0043.jp2)
  27. 5.3 Results and discussion / p75 (0044.jp2)
  28. 5.4 Conclusion / p81 (0047.jp2)
  29. References for Chapter5 / p83 (0048.jp2)
  30. Chapter6.Process and Device Performance of a Novel Shielded SBD with High Soft-error Immunity / p93 (0053.jp2)
  31. 6.1 Introduction / p93 (0053.jp2)
  32. 6.2 Principles of SSBD / p94 (0054.jp2)
  33. 6.3 Fabrication Process and Design of SSBD / p96 (0055.jp2)
  34. 6.4 Results and discussion / p98 (0056.jp2)
  35. 6.5 Conclusion / p102 (0058.jp2)
  36. References for Chapter6 / p103 (0058.jp2)
  37. Chapter7.A Novel CMOS Structure with a reduced Drain-substrate Capacitance / p113 (0063.jp2)
  38. 7.1 Introduction / p113 (0063.jp2)
  39. 7.2 Features of proposed device / p114 (0064.jp2)
  40. 7.3 Fabrication process / p115 (0064.jp2)
  41. 7.4 Results and discussion / p117 (0065.jp2)
  42. 7.5 Conclusion / p119 (0066.jp2)
  43. References for Chapter7 / p121 (0067.jp2)
  44. Chapter8.Conclusion / p129 (0071.jp2)
  45. 8.1 New findings in this thesis / p129 (0071.jp2)
  46. 8.2 Further recommendations / p131 (0072.jp2)
  47. Acknowledgement / p133 (0073.jp2)
  48. Personal History / p134 (0074.jp2)
  49. List of Publications / p135 (0074.jp2)
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各種コード

  • NII論文ID(NAID)
    500000078527
  • NII著者ID(NRID)
    • 8000000078731
  • DOI(NDL)
  • NDL書誌ID
    • 000000242841
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
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