Massively parallel model of speech-to-speech dialogue translation : the ФDmDialog system 超並列計算モデルによる音声対話翻訳 : ФDmDialogシステム

この論文をさがす

著者

    • 北野, 宏明, 1961- キタノ, ヒロアキ

書誌事項

タイトル

Massively parallel model of speech-to-speech dialogue translation : the ФDmDialog system

タイトル別名

超並列計算モデルによる音声対話翻訳 : ФDmDialogシステム

著者名

北野, 宏明, 1961-

著者別名

キタノ, ヒロアキ

学位授与大学

京都大学

取得学位

工学博士

学位授与番号

乙第7633号

学位授与年月日

1991-09-24

注記・抄録

博士論文

目次

  1. 論文目録 / (0001.jp2)
  2. Abstract / p1 (0004.jp2)
  3. Contents / (0005.jp2)
  4. 1 Introduction / p11 (0009.jp2)
  5. 1.1 Speech-to-Speech Dialogue Translation / p12 (0010.jp2)
  6. 1.2 Current Approaches to Spoken Language Translation / p14 (0011.jp2)
  7. 1.3 ΦDMDIALOG: A Model of Speech-to-Speech Translation / p16 (0012.jp2)
  8. 1.4 Dissertation Overview / p17 (0012.jp2)
  9. 2 Design Philosophy behind the ΦDMDIALOG System / p19 (0013.jp2)
  10. 2.1 Introduction / p19 (0013.jp2)
  11. 2.2 Marker-Passing / p20 (0014.jp2)
  12. 2.3 Memory-Based Approach to Natural Language Processing / p21 (0014.jp2)
  13. 2.4 Massively Parallel Computing / p27 (0017.jp2)
  14. 3 The ΦDMDIALOG System / p29 (0018.jp2)
  15. 3.1 Introduction / p29 (0018.jp2)
  16. 3.2 An Overview of the Model / p31 (0019.jp2)
  17. 3.3 Speech Input Processing / p40 (0024.jp2)
  18. 3.4 Syntactic/Semantic Parsing / p46 (0027.jp2)
  19. 3.5 Discourse Processing / p49 (0028.jp2)
  20. 3.6 Prediction from the Language Model / p55 (0031.jp2)
  21. 3.7 Cost-based Ambiguity Resolution / p56 (0032.jp2)
  22. 3.8 Interlingua with Multiple Levels of Abstraction / p59 (0033.jp2)
  23. 3.9 Generation / p61 (0034.jp2)
  24. 3.10 Simultaneous Interpretation: Generation while Parsing is in Progress / p68 (0038.jp2)
  25. 3.11 Related Works / p78 (0043.jp2)
  26. 3.12 Discussions / p78 (0043.jp2)
  27. 3.13 Conclusion / p86 (0047.jp2)
  28. 4 Implementation on the IXM2 Associative Memory Processor / p89 (0048.jp2)
  29. 4.1 Introduction / p89 (0048.jp2)
  30. 4.2 The Massively Parallel Associative Processor IXM2 / p89 (0048.jp2)
  31. 4.3 Experimental Implementation I: A Flat Pattern Model / p90 (0049.jp2)
  32. 4.4 Performance / p93 (0050.jp2)
  33. 4.5 Memory and Processor Requirements / p95 (0051.jp2)
  34. 4.6 Enhancement: Hierarchical Memory Network / p98 (0053.jp2)
  35. 4.7 Experimental Implementation II: Hierarchical Memory Network Model / p99 (0053.jp2)
  36. 4.8 Performance / p102 (0055.jp2)
  37. 4.9 Hardware Architecture for Memory-Based Parsing / p104 (0056.jp2)
  38. 4.10 Conclusion / p105 (0056.jp2)
  39. 5 Implementation on the SNAP Semantic Network Array Processor / p109 (0058.jp2)
  40. 5.1 Introduction / p109 (0058.jp2)
  41. 5.2 SNAP Architecture / p109 (0058.jp2)
  42. 5.3 Philosophy Behind DMSNAP / p112 (0060.jp2)
  43. 5.4 Implementation of DMSNAP / p114 (0061.jp2)
  44. 5.5 Linguistic Processing in DMSNAP / p117 (0062.jp2)
  45. 5.6 Performance / p124 (0066.jp2)
  46. 5.7 Conclusion / p125 (0066.jp2)
  47. 6 Unification for Massively Parallel Machines / p127 (0067.jp2)
  48. 6.1 Introduction / p127 (0067.jp2)
  49. 6.2 Architecture, Representation and Notations / p129 (0068.jp2)
  50. 6.3 Pseudo-Unification / p131 (0069.jp2)
  51. 6.4 Full-Unification / p135 (0071.jp2)
  52. 6.5 Nondestructive Unification / p138 (0073.jp2)
  53. 6.6 Typed Unification / p141 (0074.jp2)
  54. 6.7 Augmenting Unification / p142 (0075.jp2)
  55. 6.8 Efficiency of the Algorithm / p144 (0076.jp2)
  56. 6.9 Conclusion / p145 (0076.jp2)
  57. 7 Conclusion / p147 (0077.jp2)
  58. 7.1 Summary of Contributions / p147 (0077.jp2)
  59. 7.2 Future Work: The Next Move / p148 (0078.jp2)
  60. 7.3 Final Remarks / p150 (0079.jp2)
0アクセス

各種コード

  • NII論文ID(NAID)
    500000080726
  • NII著者ID(NRID)
    • 8000001002820
  • DOI(NDL)
  • NDL書誌ID
    • 000000245040
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
ページトップへ