High speed optoelectronic integrated circuits using photodiode switches フォトダイオードスイッチを用いた高速光電子集積回路に関する研究

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Author

    • 神山, 博幸 カミヤマ, ヒロユキ

Bibliographic Information

Title

High speed optoelectronic integrated circuits using photodiode switches

Other Title

フォトダイオードスイッチを用いた高速光電子集積回路に関する研究

Author

神山, 博幸

Author(Another name)

カミヤマ, ヒロユキ

University

東京大学

Types of degree

工学博士

Grant ID

甲第9011号

Degree year

1991-03-29

Note and Description

博士論文

Table of Contents

  1. Contents / (0003.jp2)
  2. Chapter1 Introduction / p1 (0005.jp2)
  3. 1.1 General / p2 (0006.jp2)
  4. 1.2 Photodetectors / p2 (0006.jp2)
  5. 1.3 Generation of Ultrashort Electrical Pulse / p4 (0008.jp2)
  6. 1.4 Optical Receiver with Amplifiers / p6 (0011.jp2)
  7. 1.5 Optical Computing / p6 (0011.jp2)
  8. 1.6 Outline of Thesis / p9 (0014.jp2)
  9. References-Chapter1 / p10 (0015.jp2)
  10. Figures-Chapter1 / p17 (0022.jp2)
  11. Chapter2 Fabricaton of High Speed MSM Photodetectors / p21 (0026.jp2)
  12. 2.1 Introduction / p22 (0027.jp2)
  13. 2.2 Design and Fabrication / p22 (0027.jp2)
  14. 2.3 Experimental Results / p25 (0030.jp2)
  15. 2.4 Numerical Analysis of MSM Photodiodes / p27 (0032.jp2)
  16. 2.5 Conclusion / p29 (0034.jp2)
  17. References-Chapter2 / p30 (0035.jp2)
  18. Figures-Chapter2 / p31 (0036.jp2)
  19. Chapter3 Generation of Very Short Electrical Pulse Using Composite MSM Photodiode / p41 (0046.jp2)
  20. 3.1 Introduction / p42 (0047.jp2)
  21. 3.2 Series-Shunt Method Using Two Optical Beams / p43 (0048.jp2)
  22. 3.3 Series-Shunt Method Using An Embedded Delay Line / p47 (0052.jp2)
  23. 3.4 Shunt Method Using Turn-On Delay of A Transistor / p52 (0057.jp2)
  24. 3.5 Conclusion / p54 (0059.jp2)
  25. References-Chapter3 / p55 (0060.jp2)
  26. Figures-Chapter3 / p56 (0061.jp2)
  27. Chapter4 Optoelectronic Logic Gates Using MSM Photodiodes / p82 (0087.jp2)
  28. 4.1 Introduction / p83 (0088.jp2)
  29. 4.2 Design and Fabrication / p83 (0088.jp2)
  30. 4.3 Experimental Results / p86 (0091.jp2)
  31. 4.4 Numerical Analysis / p90 (0095.jp2)
  32. 4.5 Proposal of Full Adder System Using OE Logic Gates / p93 (0098.jp2)
  33. 4.6 Conclusion / p97 (0102.jp2)
  34. References-Chapter4 / p98 (0103.jp2)
  35. Figures-Chapter4 / p100 (0105.jp2)
  36. Chapter5 Optoelectronic Integrated Circuit with 2DEG-FET Amplifier / p144 (0149.jp2)
  37. 5.1 Introduction / p145 (0150.jp2)
  38. 5.2 Design and Fabrication / p145 (0150.jp2)
  39. 5.3 Experimental Results / p146 (0151.jp2)
  40. 5.4 Numerical Analyisis of The PD/2DEG-FET Device / p147 (0152.jp2)
  41. 5.5 Conclusion / p149 (0154.jp2)
  42. References-Chapter5 / p149 (0154.jp2)
  43. Figures-Chapter5 / p151 (0156.jp2)
  44. Chapter6 Numerical Analysis of Optoelectronic Logic Gates / p163 (0168.jp2)
  45. 6.1 Introduction / p164 (0169.jp2)
  46. 6.2 Consideration of Component Devices for Full Adder System / p164 (0169.jp2)
  47. 6.3 Numerical Analysis of Full Adder System Using OE Logic Gates / p168 (0173.jp2)
  48. 6.4 Conclusion / p170 (0175.jp2)
  49. References-Chapter6 / p171 (0176.jp2)
  50. Figures-Chapter6 / p174 (0179.jp2)
  51. Chapter7 Conclusions / p177 (0182.jp2)
  52. Acknowledgements / p181 (0186.jp2)
  53. Publications / p183 (0188.jp2)
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Codes

  • NII Article ID (NAID)
    500000081769
  • NII Author ID (NRID)
    • 8000000081977
  • DOI(NDL)
  • NDLBibID
    • 000000246083
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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