Exploiting parallelism in cyclic pipeline computer with an optimizing compiler 最適化コンパイラによる循環パイプライン・コンピューターにおける並列化の研究

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Author

    • 佐藤, 三久 サトウ, ミツヒサ

Bibliographic Information

Title

Exploiting parallelism in cyclic pipeline computer with an optimizing compiler

Other Title

最適化コンパイラによる循環パイプライン・コンピューターにおける並列化の研究

Author

佐藤, 三久

Author(Another name)

サトウ, ミツヒサ

University

東京大学

Types of degree

理学博士

Grant ID

乙第10044号

Degree year

1991-02-21

Note and Description

博士論文

Table of Contents

  1. ABSTRACT / (0003.jp2)
  2. Contents / p1 (0005.jp2)
  3. 1 Introduction / p7 (0011.jp2)
  4. 1.1 Cyclic Pipeline Computer / p7 (0011.jp2)
  5. 1.2 FLATS2 / p8 (0012.jp2)
  6. 1.3 FLATS2 FORTRAN Compiler / p8 (0012.jp2)
  7. 1.4 Parallel Programming Model / p9 (0013.jp2)
  8. 1.5 FLATS2 project / p9 (0013.jp2)
  9. 1.6 Scope of Study in This Thesis / p10 (0014.jp2)
  10. 2 Highly pipelined Model / p11 (0015.jp2)
  11. 2.1 Models of Highly Pipelined Machines / p11 (0015.jp2)
  12. 2.2 Parallel Programming Model / p15 (0019.jp2)
  13. 2.3 Simulation / p18 (0022.jp2)
  14. 2.4 Discussion / p25 (0029.jp2)
  15. 3 A Cyclic Pipeline Computer,FLATS2 / p28 (0032.jp2)
  16. 3.1 The architecture of FLATS2 / p28 (0032.jp2)
  17. 3.2 Programming on FLATS2 / p33 (0037.jp2)
  18. 3.3 Programming Environment / p35 (0039.jp2)
  19. 4 FLATS2 FORTRAN compiler / p37 (0041.jp2)
  20. 4.1 Overview / p37 (0041.jp2)
  21. 4.2 Code Expansion Phase / p40 (0044.jp2)
  22. 4.3 Translation into Static Single Assignment Form / p41 (0045.jp2)
  23. 4.4 Redundancy Elimination / p44 (0048.jp2)
  24. 4.5 Code Reconstruction / p49 (0053.jp2)
  25. 4.6 Register Allocation / p52 (0056.jp2)
  26. 5 Loop optimization with BL Addressing / p62 (0066.jp2)
  27. 5.1 Addressing mode for Numerical Computation / p62 (0066.jp2)
  28. 5.2 Optimal Induction Variable Elimination / p64 (0068.jp2)
  29. 5.3 BL Code Generation / p74 (0078.jp2)
  30. 6 Experiments on FLATS2 / p78 (0082.jp2)
  31. 6.1 The performance of FLATS2 / p78 (0082.jp2)
  32. 6.2 The Experiments on the FLATS2 Pipeline / p81 (0085.jp2)
  33. 7 Summary and Conclusions / p88 (0092.jp2)
  34. A RUN-TIME CHECKING IN LISP BY INTEGRATING MEMORY AD_DRESSING AND RANGE CHECKING / p90 (0094.jp2)
  35. B Benchmark programs in Parallel FORTRAN / p99 (0103.jp2)
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Codes

  • NII Article ID (NAID)
    500000083371
  • NII Author ID (NRID)
    • 8000000083581
  • DOI(NDL)
  • NDLBibID
    • 000000247685
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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