Image processing using CMOS variable threshold logic on bit-mapping CAD system ビットマップCAD上におけるCMOS可変しきい値論理を用いた画像処理に関する研究
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Bibliographic Information
- Title
-
Image processing using CMOS variable threshold logic on bit-mapping CAD system
- Other Title
-
ビットマップCAD上におけるCMOS可変しきい値論理を用いた画像処理に関する研究
- Author
-
高窪, 統
- Author(Another name)
-
タカクボ, ハジメ
- University
-
上智大学
- Types of degree
-
工学博士
- Grant ID
-
甲第118号
- Degree year
-
1992-03-31
Note and Description
博士論文
Table of Contents
- Contents / p1 (0004.jp2)
- I. Introduction / p1 (0005.jp2)
- 1. Background / p1 (0005.jp2)
- 2. Purpose and Contents of Thesis / p4 (0007.jp2)
- References / p6 (0008.jp2)
- II. A Bitmap Memory Bank of Region access / p10 (0010.jp2)
- Abstract / p10 (0010.jp2)
- 1. Introduction / p11 (0010.jp2)
- 2. System Construction Employing Bitmap Memory Bank / p12 (0011.jp2)
- 3. Hardware Configuration / p15 (0012.jp2)
- 4. Software Structure / p17 (0013.jp2)
- 5. Breadboard implementation / p18 (0014.jp2)
- 6. Twin chips implementation / p20 (0015.jp2)
- 7. Evaluation of Bitmap Memory Bank / p21 (0016.jp2)
- 8. Conclusions / p23 (0015.jp2)
- References / p25 (0017.jp2)
- Figures / p26 (0018.jp2)
- III. Combination Analog and Digital Circuits using CMOS Variable Threshold Logic / p39 (0024.jp2)
- Abstract / p39 (0024.jp2)
- 1. Introduction / p40 (0025.jp2)
- 2. Design Principle of the Simple Chip / p41 (0025.jp2)
- 3. Advanced Approach / p45 (0027.jp2)
- 4. Discussion / p48 (0029.jp2)
- 5. Conclusions / p50 (0030.jp2)
- References / p51 (0030.jp2)
- Figures / p52 (0031.jp2)
- IV. A Gray Image Binarization using CMOS Variable Threshold Logic / p61 (0035.jp2)
- Abstract / p61 (0035.jp2)
- 1. Introduction / p62 (0036.jp2)
- 2. System Configuration / p63 (0036.jp2)
- 3. Principle of the Adaptive Threshold Binarization / p64 (0037.jp2)
- 4. Hardware Implementation / p67 (0038.jp2)
- 5. Results and Discussion / p70 (0040.jp2)
- 6. Conclusion / p71 (0040.jp2)
- References / p72 (0041.jp2)
- Figures / p74 (0042.jp2)
- V. An Image Tracing Approach Using CMOS Variable Threshold Logic / p83 (0046.jp2)
- Abstract / p83 (0046.jp2)
- 1. Introduction / p84 (0047.jp2)
- 2. System configuration / p85 (0047.jp2)
- 3. Principle of tracing approach / p88 (0049.jp2)
- 4. Hardware Implementation / p92 (0051.jp2)
- 5. Results and Discussion / p94 (0052.jp2)
- 6. Application Example / p95 (0052.jp2)
- 7. Conclusions / p96 (0053.jp2)
- References / p97 (0053.jp2)
- Figures / p99 (0054.jp2)
- VI. Concluding Remarks / p109 (0059.jp2)
- Acknowledgments / p112 (0061.jp2)
- List of Publications / p113 (0061.jp2)