A study on architectures of large-scale ATM switching networks for broadband ISDN 広帯域ISDNのための大規模ATMスイッチ回路網の構成に関する研究

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著者

    • 鐘, 文徳 チョン, ウエントー

書誌事項

タイトル

A study on architectures of large-scale ATM switching networks for broadband ISDN

タイトル別名

広帯域ISDNのための大規模ATMスイッチ回路網の構成に関する研究

著者名

鐘, 文徳

著者別名

チョン, ウエントー

学位授与大学

電気通信大学

取得学位

博士 (工学)

学位授与番号

甲第30号

学位授与年月日

1993-03-23

注記・抄録

博士論文

目次

  1. Contents / p4 (0010.jp2)
  2. Acknowledgement / (0007.jp2)
  3. Abstract / (0008.jp2)
  4. 1 Introduction / p1 (0018.jp2)
  5. 1.1 Integrated Communication Network / p1 (0018.jp2)
  6. 1.2 Overview of Switching Schemes / p3 (0020.jp2)
  7. 1.3 Outline of the Dissertation / p6 (0023.jp2)
  8. 2 Overview of Basic ATM Switch Architectures and Related Works / p10 (0027.jp2)
  9. 2.1 Basic ATM Switch Architectures / p11 (0028.jp2)
  10. 2.2 A Brief Survey of Related Works / p20 (0037.jp2)
  11. 3 A Non-blocking ATM Switch with R-Paths / p24 (0041.jp2)
  12. 3.1 Introduction / p24 (0041.jp2)
  13. 3.2 R-Paths-Routing Network / p26 (0043.jp2)
  14. 3.3 Switch Architecture / p31 (0048.jp2)
  15. 3.4 Contention Cell Loss Probability / p34 (0051.jp2)
  16. 3.5 Complexity Comparison / p34 (0051.jp2)
  17. 3.6 Conclusion / p37 (0054.jp2)
  18. 4 A Multichannel ATM Switch with Both Input and Output Buffers / p39 (0056.jp2)
  19. 4.1 Introduction / p39 (0056.jp2)
  20. 4.2 Switch Architecture / p40 (0057.jp2)
  21. 4.3 Channel Assignment Algorithms / p46 (0063.jp2)
  22. 4.4 Estimation of Performance Measures / p49 (0066.jp2)
  23. 4.5 Conclusion / p56 (0073.jp2)
  24. 5 An Internally Buffered Multipath ATM Switch Guaranteeing Cell Se-quence / p57 (0074.jp2)
  25. 5.1 Introduction / p57 (0074.jp2)
  26. 5.2 Switch Architecture / p60 (0077.jp2)
  27. 5.3 Maintenance of Cell Sequence / p65 (0082.jp2)
  28. 5.4 Modular Architecture of a Large Switch / p66 (0083.jp2)
  29. 5.5 Application in Multichannel Bandwidth Allocation Environment / p68 (0085.jp2)
  30. 5.6 Performance Analysis / p70 (0087.jp2)
  31. 5.7 Conclusion / p78 (0095.jp2)
  32. 6 A Recursive Copy Network for Large-Scale Multicast ATM Switching:Architecture and Principle / p80 (0097.jp2)
  33. 6.1 Introduction / p80 (0097.jp2)
  34. 6.2 Architecture of Recursive Copy Network / p83 (0100.jp2)
  35. 6.3 Copy Algorithms / p87 (0104.jp2)
  36. 6.4 Preservation of Cell Sequence / p90 (0107.jp2)
  37. 6.5 Configuration of Large Modular Multicast ATM Switches / p91 (0108.jp2)
  38. 6.6 Performance Estimation / p95 (0112.jp2)
  39. 6.7 Conclusion / p100 (0117.jp2)
  40. 7 A Copy Network with Output Reservation for Large-Scale MulticastATM Switching / p102 (0119.jp2)
  41. 7.1 Introduction / p102 (0119.jp2)
  42. 7.2 Non-blocking Property of BBN / p103 (0120.jp2)
  43. 7.3 Architecture of Copy Network with Output Reservation / p106 (0123.jp2)
  44. 7.4 Token Passing Scheme / p108 (0125.jp2)
  45. 7.5 Copy Algorithm / p109 (0126.jp2)
  46. 7.6 Performance Estimation / p113 (0130.jp2)
  47. 7.7 Conclusion / p121 (0138.jp2)
  48. 8 Concluding Remarks and Future Studies / p122 (0139.jp2)
  49. Appendix / p126 (0143.jp2)
  50. A Block Level Description of the Index Allocation Network / p126 (0143.jp2)
  51. B Brief Description of the Max-Index Selector / p128 (0145.jp2)
  52. C Proof of Theorem 7.2.1 / p130 (0147.jp2)
  53. Bibliography / p132 (0149.jp2)
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各種コード

  • NII論文ID(NAID)
    500000094923
  • NII著者ID(NRID)
    • 8000000095149
  • DOI(NDL)
  • NDL書誌ID
    • 000000259237
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
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