Meta-programming in logic 論理型メタプログラミング

この論文をさがす

著者

    • 藤田, 博 フジタ, ヒロシ

書誌事項

タイトル

Meta-programming in logic

タイトル別名

論理型メタプログラミング

著者名

藤田, 博

著者別名

フジタ, ヒロシ

学位授与大学

東京大学

取得学位

博士 (工学)

学位授与番号

乙第10452号

学位授与年月日

1991-12-12

注記・抄録

博士論文

目次

  1. Contents / p3 (0004.jp2)
  2. I Introduction / p3 (0011.jp2)
  3. 1 Introduction / p5 (0012.jp2)
  4. 2 Preliminaries / p9 (0014.jp2)
  5. 2.1 Logic Programs / p9 (0014.jp2)
  6. 2.2 Meta-Programming / p10 (0015.jp2)
  7. 2.3 Partial Evaluation / p11 (0015.jp2)
  8. 2.4 Guarded Horn Clauses / p14 (0017.jp2)
  9. 2.5 Parallel Logic Programming / p15 (0017.jp2)
  10. II Efficient Meta-Programming in Logic / p19 (0019.jp2)
  11. 3 Deriving An Efficient Production System / p21 (0020.jp2)
  12. 3.1 Introduction / p21 (0020.jp2)
  13. 3.2 Simple Production System Interpreter / p22 (0021.jp2)
  14. 3.3 Working Memory Driven PS Interpreter / p24 (0022.jp2)
  15. 3.4 Performance Evaluation / p28 (0024.jp2)
  16. 3.5 Comparison with Related Research / p32 (0026.jp2)
  17. 3.6 Concluding Remarks / p33 (0026.jp2)
  18. 4 Enhanced Partial Evaluation / p35 (0027.jp2)
  19. 4.1 Introduction / p35 (0027.jp2)
  20. 4.2 How to Obtain Further Speedup / p36 (0028.jp2)
  21. 4.3 Automating Partial Evaluation / p43 (0031.jp2)
  22. 4.4 Concluding Remarks / p50 (0035.jp2)
  23. 5 Compiler Generation / p53 (0036.jp2)
  24. 5.1 Introduction / p53 (0036.jp2)
  25. 5.2 Development of the Partial Evaluator / p55 (0037.jp2)
  26. 5.3 Compilation,Compiler and Compiler Generator / p63 (0041.jp2)
  27. 5.4 Incremental Compilation / p71 (0045.jp2)
  28. 5.5 Performance Results / p76 (0048.jp2)
  29. 5.6 Further Application / p79 (0049.jp2)
  30. 5.7 Concluding Remarks / p81 (0050.jp2)
  31. 6 Partial Evaluation of Parallel Programs / p83 (0051.jp2)
  32. 6.1 Introduction / p83 (0051.jp2)
  33. 6.2 Overview of the UR-set / p84 (0052.jp2)
  34. 6.3 Partial Evaluation of GHC Programs / p86 (0053.jp2)
  35. 6.4 Examples of FGHC Partial Evaluation / p89 (0054.jp2)
  36. 6.5 Partial Evaluation with Constraints / p97 (0058.jp2)
  37. 6.6 Examples Solved with Constraints / p99 (0059.jp2)
  38. 6.7 Relation to Other Research / p101 (0060.jp2)
  39. 6.8 Concluding Remarks / p103 (0061.jp2)
  40. III Meta-Programming in Parallel Logic Languages / p105 (0062.jp2)
  41. 7 Parallel Unification and Its Applications / p107 (0063.jp2)
  42. 7.1 Introduction / p107 (0063.jp2)
  43. 7.2 Parallel Unification Algorithm / p108 (0064.jp2)
  44. 7.3 Parallel Unification Program in GHC / p110 (0065.jp2)
  45. 7.4 Flat-GHC Meta-Interpreter / p117 (0068.jp2)
  46. 7.5 Parallel Knuth-Bendix Algorithm / p121 (0070.jp2)
  47. 7.6 Performance Results / p127 (0073.jp2)
  48. 7.7 Concluding Remarks / p130 (0075.jp2)
  49. 8 KL1 Technology Theorem Prover / p133 (0076.jp2)
  50. 8.1 Introduction / p133 (0076.jp2)
  51. 8.2 Meta-Programming in KL1 / p134 (0077.jp2)
  52. 8.3 Model Generation Method / p135 (0077.jp2)
  53. 8.4 MGTP for Ground Model / p137 (0078.jp2)
  54. 8.5 Avoiding Redundancy / p141 (0080.jp2)
  55. 8.6 Parallel Execution / p148 (0084.jp2)
  56. 8.7 Concluding Remarks / p151 (0085.jp2)
  57. 9 First-Order Theorem Prover in KL1 / p155 (0087.jp2)
  58. 9.1 Introduction / p155 (0087.jp2)
  59. 9.2 Features for Solving Hard Horn Problems / p156 (0088.jp2)
  60. 9.3 Variables and Unification Revisited / p158 (0089.jp2)
  61. 9.4 Further Improvements on MGTP kernel / p160 (0090.jp2)
  62. 9.5 Performance Comparison / p164 (0092.jp2)
  63. 9.6 Concluding Remarks / p165 (0092.jp2)
  64. IV Conclusion / p167 (0093.jp2)
  65. 10 Conclusion / p169 (0094.jp2)
  66. 10.1 Contribution / p169 (0094.jp2)
  67. 10.2 Future Research / p172 (0096.jp2)
  68. Appendix / p175 (0097.jp2)
  69. Proof of Theorem 7.1 / p175 (0097.jp2)
  70. Bibliography / p179 (0099.jp2)
  71. Publications by the Author / p189 (0104.jp2)
0アクセス

各種コード

  • NII論文ID(NAID)
    500000098096
  • NII著者ID(NRID)
    • 8000000098325
  • DOI(NDL)
  • NDL書誌ID
    • 000000262410
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
ページトップへ