Two-mode channel FET (TMT) for low-noise and high-power applications 低雑音・高出力用2モードチャネル電界効果型トランジスタ
この論文にアクセスする
この論文をさがす
著者
書誌事項
- タイトル
-
Two-mode channel FET (TMT) for low-noise and high-power applications
- タイトル別名
-
低雑音・高出力用2モードチャネル電界効果型トランジスタ
- 著者名
-
澤田, 稔
- 著者別名
-
サワダ, ミノル
- 学位授与大学
-
大阪大学
- 取得学位
-
博士 (工学)
- 学位授与番号
-
乙第6859号
- 学位授与年月日
-
1996-02-22
注記・抄録
博士論文
目次
- Abstract / p1 (0004.jp2)
- Contents / p3 (0008.jp2)
- 1.Introduction / p1 (0012.jp2)
- 1.1 Background and Purpose of This Investigation / p2 (0013.jp2)
- 1.2 Outline of Investigations for Existing Devices and Problems Facing These Devices as a Fundamental Device for a Single-Chip Unified MMIC / p4 (0015.jp2)
- 1.3 Construction of This Report / p8 (0019.jp2)
- References / p13 (0024.jp2)
- 2.TMT Structure Design / p17 (0028.jp2)
- 2.1 Introduction / p18 (0029.jp2)
- 2.2 Newly Designed TMT Structure / p19 (0030.jp2)
- 2.3 Calculation Method for Electron Probability Density Distribution / p24 (0035.jp2)
- 2.4 Electron Probability Density Distribution in the Channel / p28 (0039.jp2)
- 2.5 Conclusion / p33 (0044.jp2)
- References / p34 (0045.jp2)
- 3.TMT Fundamental Device Characteristics / p35 (0046.jp2)
- 3.1 Introduction / p36 (0047.jp2)
- 3.2 TMT Fundamental Device Characteristics / p36 (0047.jp2)
- 3.3 Relation between Low-Noise Performance and Electron Confinement in the Channel of a TMT in a Low-Drain-Current Condition / p43 (0054.jp2)
- 3.4 Conclusion / p50 (0061.jp2)
- References / p52 (0063.jp2)
- 4.Planar-Type TMT / p55 (0066.jp2)
- 4.1 Introduction / p56 (0067.jp2)
- 4.2 Annealing Process and Effect for a Planar-Type TMT / p58 (0069.jp2)
- 4.3 A Planar-Type TMT Suitable for MMICs with Transmission and Reception Blocks / p74 (0085.jp2)
- 4.4 Improvement of Device Performance for a Planar-Type TMT / p81 (0092.jp2)
- 4.5 Conclusion / p88 (0099.jp2)
- References / p90 (0101.jp2)
- 5.Summary / p93 (0104.jp2)
- 6.Appendix A:Low-Noise Performance for a Heterojunction FET with a Highly Doped Channel / p99 (0110.jp2)
- 6.1 Introduction / p100 (0111.jp2)
- 6.2 Device Structure and Device Fabrication Process / p100 (0111.jp2)
- 6.3 Device Characteristics / p102 (0113.jp2)
- 6.4 Conclusion / p108 (0119.jp2)
- References / p110 (0121.jp2)
- 7.Appendix B:Modulation Doped Channel Design / p111 (0122.jp2)
- 7.1 Introduction / p112 (0123.jp2)
- 7.2 Suitable Channel Design for an AlGaAs/GaAs HEMT and an AlGaAs/InGaAs HEMT / p112 (0123.jp2)
- 7.3 Suitable Channel Design for an InAlAs/InGaAs HEMT / p123 (0134.jp2)
- 7.4 Conclusion / p132 (0143.jp2)
- References / p133 (0144.jp2)
- 8.Appendix C:Silicon Nitride Films for Annealing Encapsulant / p135 (0146.jp2)
- 8.1 Introduction / p136 (0147.jp2)
- 8.2 ECR-plasma-CVD Apparatus and Method of Film Formation / p137 (0148.jp2)
- 8.3 Methods of Experiments and Evaluations / p139 (0150.jp2)
- 8.4 Experimental Results / p140 (0151.jp2)
- 8.5 Conclusion / p153 (0164.jp2)
- References / p155 (0166.jp2)
- List of publications / (0168.jp2)
- International Conferences / (0169.jp2)
