Completeness on multiple-valued logical functions realized by asynchronous sequential circuits 非同期式順序回路によって定義される多値論理関数の完全性について
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Bibliographic Information
- Title
-
Completeness on multiple-valued logical functions realized by asynchronous sequential circuits
- Other Title
-
非同期式順序回路によって定義される多値論理関数の完全性について
- Author
-
佐藤, 尚
- Author(Another name)
-
サトウ, ヒサシ
- University
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学習院大学
- Types of degree
-
博士 (理学)
- Grant ID
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乙第79号
- Degree year
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1996-03-09
Note and Description
博士論文
application/pdf
Table of Contents
- Contents / p1 (0003.jp2)
- 1 Introduction / p2 (0004.jp2)
- 2 Asynchronous Circuit / p8 (0010.jp2)
- 3 Output Stability / p11 (0013.jp2)
- 4 Realization of Logical Functions by Asynchronous Sequential Circuits / p13 (0015.jp2)
- 4.1 Realization / p13 (0015.jp2)
- 4.2 Initialization / p14 (0016.jp2)
- 5 Classical Completeness Problem / p15 (0017.jp2)
- 5.1 Functional Completeness / p15 (0017.jp2)
- 5.2 Examples of Complete sets / p15 (0017.jp2)
- 5.3 Completeness Criteria / p20 (0022.jp2)
- 5.4 Completeness under“loop-free” / p23 (0025.jp2)
- 6 Completeness under the General Initialization Assumption / p25 (0027.jp2)
- 7 Completeness for Restricted Sequential Circuit under the General Initialization Assumption / p32 (0034.jp2)
- 7.1 GR-completeness / p32 (0034.jp2)
- 7.2 GR-completeness criterion for the binary case / p34 (0036.jp2)
- 8 Completeness under the Initialization-by-Input Assumption / p40 (0042.jp2)
- 8.1 NS-completeness / p40 (0042.jp2)
- 8.2 Examples of NS-complete and NS-incomplete sets / p42 (0044.jp2)
- 8.3 NS-completeness criterion for the binary case / p46 (0048.jp2)
- References / p53 (0055.jp2)
