Code generation and high-level synthesis for embedded systems 組込みシステムのためのコード生成と高位合成

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Author

    • 冨山, 宏之 トヤマ, ヒロユキ

Bibliographic Information

Title

Code generation and high-level synthesis for embedded systems

Other Title

組込みシステムのためのコード生成と高位合成

Author

冨山, 宏之

Author(Another name)

トヤマ, ヒロユキ

University

九州大学

Types of degree

博士(工学)

Grant ID

甲第4783号

Degree year

1999-03-25

Note and Description

博士論文

Table of Contents

  1. Abstract / p1 (0003.jp2)
  2. Contents / p3 (0004.jp2)
  3. 1 Introduction / p1 (0006.jp2)
  4. 1.1 Background / p1 (0006.jp2)
  5. 1.2 Goal of This Research / p4 (0008.jp2)
  6. 1.3 Contributions of This Research / p5 (0008.jp2)
  7. 1.4 Organization of This Thesis / p6 (0009.jp2)
  8. 2 Embedded System Design / p9 (0010.jp2)
  9. 2.1 Introduction / p9 (0010.jp2)
  10. 2.2 Embedded System Architecture / p10 (0011.jp2)
  11. 2.3 Design Methodology / p11 (0011.jp2)
  12. 2.4 Code Generation / p13 (0012.jp2)
  13. 2.5 High-Level Synthesis / p15 (0013.jp2)
  14. 2.6 Conclusions / p16 (0014.jp2)
  15. 3 Code Generation for Datapath Width Optimization / p19 (0015.jp2)
  16. 3.1 Introduction / p19 (0015.jp2)
  17. 3.2 Datapath Width Optimization / p20 (0016.jp2)
  18. 3.3 The Valen-C Language / p27 (0019.jp2)
  19. 3.4 The Valen-C Retargetable Compiler / p29 (0020.jp2)
  20. 3.5 Experiments / p32 (0022.jp2)
  21. 3.6 Conclusions / p36 (0024.jp2)
  22. 4 Global Code Placement for High-Performance and Low-Power Memories / p37 (0024.jp2)
  23. 4.1 Introduction / p37 (0024.jp2)
  24. 4.2 Related Work / p39 (0025.jp2)
  25. 4.3 A Simplified Code Placement Method / p40 (0026.jp2)
  26. 4.4 A Refined Code Placement Method / p53 (0032.jp2)
  27. 4.5 Conclusions / p59 (0035.jp2)
  28. 5 Local Instruction Scheduling for Low-Power Memories / p61 (0036.jp2)
  29. 5.1 Introduction / p61 (0036.jp2)
  30. 5.2 Related Work / p62 (0037.jp2)
  31. 5.3 Problem Definition / p63 (0037.jp2)
  32. 5.4 Scheduling Algorithms / p67 (0039.jp2)
  33. 5.5 Experiments / p73 (0042.jp2)
  34. 5.6 Conclusions / p79 (0045.jp2)
  35. 6 High-Level Synthesis for Manufacturability / p81 (0046.jp2)
  36. 6.1 Introduction / p81 (0046.jp2)
  37. 6.2 Functional Unit Modeling / p84 (0048.jp2)
  38. 6.3 Module Selection / p85 (0048.jp2)
  39. 6.4 Statistical Delay Analysis / p98 (0055.jp2)
  40. 6.5 Module Binding / p107 (0059.jp2)
  41. 6.6 Conclusions / p113 (0062.jp2)
  42. 7 Conclusions / p117 (0064.jp2)
  43. 7.1 Summary of Contributions / p117 (0064.jp2)
  44. 7.2 Future Directions / p119 (0065.jp2)
  45. Acknowledgment / p121 (0066.jp2)
  46. Bibliography / p123 (0067.jp2)
  47. List of Publications by the Author / p131 (0071.jp2)
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Codes

  • NII Article ID (NAID)
    500000171759
  • NII Author ID (NRID)
    • 8000000172033
  • DOI(NDL)
  • NDLBibID
    • 000000336073
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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