Fully Balanced Circuit Designs Having Zero Common-Mode Gain 同相利得が零である平衡型回路の設計

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Author

    • 鄭, 文在 ジョン, ムンジェ

Bibliographic Information

Title

Fully Balanced Circuit Designs Having Zero Common-Mode Gain

Other Title

同相利得が零である平衡型回路の設計

Author

鄭, 文在

Author(Another name)

ジョン, ムンジェ

University

東京工業大学

Types of degree

博士 (工学)

Grant ID

甲第4342号

Degree year

2000-03-26

Note and Description

博士論文

資料形態 : テキストデータ プレーンテキスト

コレクション : 国立国会図書館デジタルコレクション > デジタル化資料 > 博士論文

Table of Contents

  1. 論文目録
  2. Table of Contents
  3. 1 General Introduction
  4. 1.1 Background and Motivation
  5. 1.2 Organization of the Dissertation
  6. 2 Fully Balanced Circuit Designs:Some Fundamentals
  7. 2.1 Single-Ended versus Fully Balanced Designs
  8. 2.2 Conventional Common-Mode Feedback Circuits
  9. 2.3 Conclusions
  10. 3 New Fully Balanced Circuit Structure
  11. 3.1 Principle
  12. 3.2 Simplification conditions
  13. 3.3 Stability
  14. 3.4 Component Mismatch
  15. 3.5 Conclusions
  16. 4 Applications to Fully Balanced Circuit Designs
  17. 4.1 Basic Amplifier Design
  18. 4.2 Integrator Design
  19. 4.3 Voltage Amplifier Design
  20. 4.4 Operational Amplifier Design
  21. 4.5 Filter Designs
  22. 4.6 Conclusions
  23. 5 Application Example to a Channel-Select Filter
  24. 5.1 Motivation
  25. 5.2 Specifications
  26. 5.3 Filter Architecture
  27. 5.4 Filter Design
  28. 5.5 Overall Filter Characteristics and Evaluations
  29. 5.6 Conclusions
  30. 6 General Conclusions
  31. Bibliography
  32. List of Papers of the Author
2access

Codes

  • NII Article ID (NAID)
    500002109385
  • NII Author ID (NRID)
    • 8000002673489
  • DOI(NDL)
  • Text Lang
    • eng
  • NDLBibID
    • 000000392976
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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