Wafer scale integration : proceedings of a workshop held in Southampton from 10 July to 12 July 1985
著者
書誌事項
Wafer scale integration : proceedings of a workshop held in Southampton from 10 July to 12 July 1985
Hilger, c1986
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注記
Includes bibliographies and index
内容説明・目次
内容説明
This book, the first to deal wholly with the topic of wafer scale integration, is the edited proceedings of a workshop held at the University of Southampton in July 1985. As the first international meeting held on this subject it attracted many participants from Europe and the United States. The meeting was particularly timely as there has recently been a renewed interest in research and commercial exploitation of wafer scale integration. The papers presented in the book cover the whole range of topics important in wafer scale integration, beginning with a critical review of fault-tolerant chips and wafer scale integration. Sections on general problems and interconnection strategies follow. There are then six papaers on architectures and four on restructurable very large scale integration. The book concludes with three reviews of different aspects of testability.
目次
A critical review of fault-tolerant chips and WSI: General problems: Graph-theoretic approaches to fault-tolerant WSI processor arrays. An analysis of the interconnection problem for WSI. Wafer scale integration using discretionary micro-transmission line interconnections. A power distribution stategy for WSI. Clock distribution techniques for WSI. Interconnection strategies: Redundancy strategies for WSI. Interconnection strategies for the WASP device. A programmable switch matrix for the wafer scale integration of a processor array. Wafer scale integration based on self-organisation. fault-tolerant wafer scale architectures using large crossbar switch arrays. Automatic partitioning for yeild enhancement. Architectures: WASP - a WSI associative string processor for structured data processing. The reconfigurable processor array - an architecture in need of WSI. Reduction on a wafer. COBWEB - a reduction architecture. A WSI system for the computation of the two-dimensional fast Fourier transform. The implementation of a two-dimensional redundancy scheme in a wafer scale high-speed disk memory. Restructurable very large scale integration: The RVLSI approach to wafer scale integration. Laser-linking technology for RVSLI. Computer aided design and testing for RVLSI. Applications of RVLSI to signal processing. Testability: A test method for a parameterised cell disign approach to fault-tolerant VLSI and wafer scale integration. Token-triggered systolic diagnosis of wafer scale arrays. Fault tolerance in a large bit-level systolic array.
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