Assessing fault model and test quality
著者
書誌事項
Assessing fault model and test quality
（The Kluwer international series in engineering and computer science, SECS 157 . VLSI,
Kluwer Academic, c1992
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注記
Includes bibliographical references (p. [109]-125) and index
内容説明・目次
内容説明
For many years, the dominant fault model in automatic test pattern gen eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.
目次
kS FormS=k,S?k.- 7.5.5 Symmetric Functions with M-sets Integrally Divisible by a Constantc(not Divisible byc).- 7.6 Uniqueness Argument.- 7.7 OBDDs for Tree Circuits.- 7.8 OBDD Size Summary.- 8. Difference Propagation.- 8.1 The Development of Difference Propagation.- 8.2 Deriving the Input-Output Relationships.- 8.3 The Difference Propagation Algorithm.- 8.4 The Efficiency of Differences.- 8.5 Using Functional Decomposition.- 8.5.1 "Random" Decomposition.- 8.5.2 Threshold Decomposition.- 8.5.3 Minimum Circuit Width Approach.- 8.5.4 Empirical Comparison of Decomposition Techniques.- 9. Fault Model Behavior.- 9.1 Selection of Fault Models and Fault Sets.- 9.1.1 Stuck-at Fault Sets.- 9.1.2 Bridging Fault Sets.- 9.2 Fault Behavior Results and Analysis.- 9.2.1 Stuck-at Fault Behavior.- 9.2.2 Bridging Fault Behavior.- 10.The Contributions of Con/Obs to Test.- 10.1 Motivation to Study Con/Obs.- 10.2 Definitions of Con/Obs.- 10.3 Generating Con/Obs Information.- 10.3.1 Calculating Fault Controllability Functions.- 10.3.2 Calculating Fault Observability Functions.- 10.4 Con/Obs Results and Analysis.- 10.5 Con/Obs Summary.- 11.Analyzing Test Performance.- 11.1 Defect Level Motivation.- 11.2 ATPG Model Development.- 11.3 Fault Set Selectability.- 11.4 Probabilistic Non-Target Defect Coverage.- 11.5 Faults Sets.- 11.6 Test Performance Results.- 11.7 Implications to Defect Level.- 12. Conclusions.- 13.Suggestions for Future Research.- 13.1 Extensions to OBDD Size Research.- 13.2 Extensions to Difference Propagation.- 13.3 Extensions to Test Quality Research.- 13.4 Using Ordered Partial Decision Diagrams.- 13.5 General Extensions.
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