VLSI 93 : proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September 1993
著者
書誌事項
VLSI 93 : proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September 1993
（IFIP transactions, A . Computer science and technology ; 42）
North-Holland, 1994
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
VLSI (Very Large Scale Integration) results from the optimum integration of a broad range of technologies and disciplines, including architectures, software, circuits and semiconductor physics. VLSI is fundamentally interdisciplinary in nature and this will become increasingly so in the future as the requirements for greater complexity and performance grow. With the general tendency for specialisation of human skills, the goal of encompassing all the knowledge necessary to make such progress is indeed challenging. This volume provides a broad ranging interdisciplinary exploration of VLSI by specialists and aims to stimulate further research in this exciting area.
目次
- Part 1 Layout synthesis: post-placement technology mapping, D. Brasen and A. Ginetti
- optimal layout recycling based on graph theoretic linear programming approach, Y. Shigehiro et al
- a family of module generators for the layout synthesis of I/O buffers, K.M. Nguyen and M.C. Lefebvre
- A 45 degree compaction algorithm handling overconstraints, L. Ladage and G. Lodde. Part 2 Special purpose architectures: invited paper - personal communicators - a better way to stay in touch, H.M. Hauser
- design of a GaAs redundant divider, I. Moussa et al
- an ASIC array architecture for the DITPOS algorithm, P.M.R. Jensen
- performance of object caching for object-oriented systems, J.M. Chang and E.F. Gehringer
- a VLSI circuit for on-line polynomial computing - application to exponential, trigonometric and hyperbolic functions, A. Skaf et al. Part 3 Design for testability: self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design, M. Gossel and E.S. Sogomonyan
- partitioning and hierarchical description of self-testable designs, A.P. Stroele
- test of single fault tolerant controllers in VLSI circuits, R. Leveugle
- a C-testable parallel multiplier using differential cascode voltage switch (DCVS) logic, W.A. Waller and S.M. Aziz. Part 4 Image processing: invited paper - opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensors, D. Poussart
- single board image processing unit for vehicle guidance, J. Schonfeld and P. Pirsch
- implementation of the volume rendering algorithm using a low-power design-style, J. Smit et al
- design of a dedicated neural network on silicon - application to optical character recognition, D. Jacquet and G. Saucier. Part 5 High performance processors: invited paper - ARM6 - processor design for high performance at low power, M. Muller
- a new method for retiming multi-functional processing units, A. Van der Werf et al
- a transformational approach to asynchronous high-level synthesis, G. Gopalkrishnan and V. Akella
- a micropipelined ARM, S.B. Furber et al
- a high performance RISC microprocessor, F. Poirier et al. Part 6 Low level models: probabilistic power consumption estimation in digital circuits, W. Rothig et al
- solving the partial differential equations of transmission lines with wave digital filters, M. Erbar et al
- parallel harmonic balance, M. Schneider et al
- estimating lower hardware bounds in high-level synthesis, N. Wehn et al. Part 7 Multichip modules: invited paper - ultra high speed CMOS design, C. Svensson and J. Yuan
- the implementation of a MCM associative string processor, C.M. Habiger and I.P. Jalowiecki
- superconductive interconnections in multi-chip modules, B. Cabon et al. Part 8 Routing: a multilayer channel router based on optimal multilayer net assignment, M.S. Tanaka and M. Ishikawa. (Part contents).
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