Logic synthesis for field-programmable gate arrays
著者
書誌事項
Logic synthesis for field-programmable gate arrays
（The Kluwer international series in engineering and computer science, SECS 324 . VLSI,
Kluwer Academic, c1995
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注記
Bibliography: p. 409-418
Includes index
内容説明・目次
内容説明
Short turnaround has become critical in the design of electronic systems. Software- programmable components such as microprocessors and digital signal processors have been used extensively in such systems since they allow rapid design revisions. However, the inherent performance limitations of software-programmable systems mean that they are inadequate for high-performance designs. Designers thus turned to gate arrays as a solution. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented. The growing complexity of the logic circuits that can be packed onto an FPGA chip means that it has become important to have automatic synthesis tools that implement logic functions on these architectures. Logic Synthesis for Field-Programmable Gate Arrays describes logic synthesis for both look-up table (LUT) and multiplexor-based architectures, with a balanced presentation of existing techniques together with algorithms and the system developed by the authors.
Audience: A useful reference for VLSI designers, developers of computer-aided design tools, and anyone involved in or with FPGAs.
目次
Preface. Part I: Introduction. 1. Introduction. 2. Background. Part II: Look-up table (LUT) architectures. 3. Mapping computational logic. 4. Logic optimization. 5. Complexity issues. 6. Mapping sequential logic. 7. Performance directed synthesis. Part III: Multiplexor-based architectures. 8. Mapping combinational logic. Part IV: Conclusions. 10. Conclusions. References. Index.
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