Interaction between compilers and computer architectures

著者

書誌事項

Interaction between compilers and computer architectures

edited by Gyungho Lee, Pen-Chung Yew

(The Kluwer international series in engineering and computer science, SECS 613)

Kluwer Academic Publishers, c2001

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注記

Includes bibliographical references and indexes

内容説明・目次

内容説明

Effective compilers allow for a more efficient execution of application programs for a given computer architecture, while well-conceived architectural features can support more effective compiler optimization techniques. A well thought-out strategy of trade-offs between compilers and computer architectures is the key to the successful designing of highly efficient and effective computer systems. From embedded micro-controllers to large-scale multiprocessor systems, it is important to understand the interaction between compilers and computer architectures. The goal of the Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT) is to promote new ideas and to present recent developments in compiler techniques and computer architectures that enhance each other's capabilities and performance. Interaction Between Compilers and Computer Architectures is an updated and revised volume consisting of seven papers originally presented at the Fifth Workshop on Interaction between Compilers and Computer Architectures (INTERACT-5), which was held in conjunction with the IEEE HPCA-7 in Monterrey, Mexico in 2001. This volume explores recent developments and ideas for better integration of the interaction between compilers and computer architectures in designing modern processors and computer systems. Interaction Between Compilers and Computer Architectures is suitable as a secondary text for a graduate level course, and as a reference for researchers and practitioners in industry.

目次

  • Preface
  • Gyungho Lee, Pen-Chung Yew. 1. EquiMax Optimal Scheduling Formulation
  • S.-A.-A. Touati. 2. An Efficient Semi-Hierarchical Array Layout
  • N.P. Drakenberg, et al. 3. Impact of Tile-Size Selection for Skewed Tiling
  • Yonghong Song, Zhiyuan Li. 4. Improving Software Pipelining by Hiding Memory Latency
  • M. Bedy, et al. 5. Register Allocation for Embedded System
  • Heung-Bok Lee, et al. 6. Is Compiling for Performance == Compiling for Power?
  • M. Valluri, L.K. John. 7. A Technology-Scalable Architecture for Fast Clocks and High ILP
  • K. Sankaralingam, et al. Topic Index. Author Index.

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詳細情報

  • NII書誌ID(NCID)
    BA53778715
  • ISBN
    • 0792373707
  • 出版国コード
    us
  • タイトル言語コード
    eng
  • 本文言語コード
    eng
  • 出版地
    Boston
  • ページ数/冊数
    xi, 139 p.
  • 大きさ
    25 cm
  • 親書誌ID
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