Verilog-2001 : a guide to the new features of the Verilog hardware description language
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書誌事項
Verilog-2001 : a guide to the new features of the Verilog hardware description language
（The Kluwer international series in engineering and computer science）
Kluwer Academic Publishers, c2002
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Verilog 2001
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内容説明・目次
内容説明
by Phil Moorby The Verilog Hardware Description Language has had an amazing impact on the mod em electronics industry, considering that the essential composition of the language was developed in a surprisingly short period of time, early in 1984. Since its introduc tion, Verilog has changed very little. Over time, users have requested many improve ments to meet new methodology needs. But, it is a complex and time consuming process to add features to a language without ambiguity, and maintaining consistency. A group of Verilog enthusiasts, the IEEE 1364 Verilog committee, have broken the Verilog feature doldrums. These individuals should be applauded. They invested the time and energy, often their personal time, to understand and resolve an extensive wish-list of language enhancements. They took on the task of choosing a feature set that would stand up to the scrutiny of the standardization process. I would like to per sonally thank this group. They have shown that it is possible to evolve Verilog, rather than having to completely start over with some revolutionary new language. The Verilog 1364-2001 standard provides many of the advanced building blocks that users have requested. The enhancements include key components for verification, abstract design, and other new methodology capabilities. As designers tackle advanced issues such as automated verification, system partitioning, etc., the Verilog standard will rise to meet the continuing challenge of electronics design.
目次
- Foreword
- P. Moorby. Introduction. What's new in Verilog-2001. 1. Combined port and data type declarations. 2. ANSI C style module declarations. 3. Module port parameter lists. 4. ANSI C style UDP declarations. 5. Variable initial value at declaration. 6. ANSI C style task/function declarations. 7. Automatic (re-entrant) tasks. 8. Automatic (recursive) functions. 9. Constant functions. 10. Comma separated sensitivity lists. 11. Combinational logic sensitivity lists. 11. Combinational logic sensitivity lists. 12. Implicit nets for continuous assignments. 13. Disabling implicit net declarations. 14. Variable vector part selects. 15. Multidimensional arrays. 16. Arrays of net and real data types. 17. Array bit and part selects. 18. Signed reg, net and port declarations. 19. Signed based integer numbers. 20. Signed functions. 21. Sign conversion system functions. 22. Arithmetic shift operators. 23. Assignment width extension past 32 bits. 24. Power operator. 25. Attributes. 26. Sized and typed parameter constants. 27. Explicit in-line parameter redefinition. 28. Fixed local parameters. 29. Standard random number generator. 30. Extended number of open files. 31. Enhanced file I/O. 32. String read and write system tasks. 33. Enhanced invocation option testing. 34. Enhanced conditional compilation. 35. Source file and line compiler directive. 36. Generate blocks. 37. Configurations. 38. On-detect pulse error propagation. 39. Negative pulse detection. 40. Enhanced input timing checks. 41. Negative input timing constraints. 42. Enhanced SDF file support. 43. Extended VCD files. 44. Enhanced PLA system tasks. 45. Enhanced Verilog PLI support. Appendices. Index.
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