Closing the gap between ASIC & custom : tools and techniques for high-performance ASIC design
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書誌事項
Closing the gap between ASIC & custom : tools and techniques for high-performance ASIC design
Kluwer Academic Publishers, c2002
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内容説明・目次
内容説明
by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy's comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.
目次
- Preface. List of trademarks. 1. Introduction and Overview of the Book
- D. Chinnery, K. Keutzer. Contributing Factors. 2. Improving Performance through Microarchitecture
- D. Chinnery, K. Keutzer. 3. Reducing the Timing Overhead
- D. Chinnery, K. Keutzer. 4. High-Speed Logic, Circuits, Libraries and Layout
- A. Chang, et al. 5. Finding Peak Performance in a Process
- D. Chinnery, K. Keutzer. Design Techniques. 6. Physical Prototyping Plans for High Performance
- M. Courtoy, et al. 7. Automatic Replacement of Flip-Flops by Latches in ASIC's
- D. Chinnery, et al. 8. Useful-Skew Clock Synthesis Boosts ASIC Performance
- W. Dai, D. Staepelaere. 9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
- M. Cote, P. Hurat. 10. Design Optimization with Automated Flex-Cell Creation
- D. Bhattacharya, V. Boppana. 11. Exploiting Structure and Managing Wires to Increase Density and Performance
- A. Chang, W.J. Dally. 12. Semi-Custom Methods in a High-Performance Microprocessor Design
- G.A. Northrop. 13. Controlling Uncertainty in High Frequency Designs
- S.E. Rich, et al. 14. Increasing Circuit Performance through Statistical Design Techniques
- M. Orshansky. Design Examples. 15. Achieving 550MHz in a Standard Cell ASIC Methodology
- D. Chinnery, et al. 16. The iCORE (R) 520MHz Synthesizable CPU Core
- N. Richardson, et al. 17. Creating Synthesizable ARM Processors with Near Custom Performance
- D. Flynn, M.Keating.
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