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IEICE transactions on information and systems The Institute of Electronics, Information and Communication Engineers E87-D(3) (20040301)

COVER Full Text: CiNii
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS Editorial Committee Full Text: CiNii
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS Information for Authors Full Text: CiNii
CONTENTS Full Text: CiNii
Editorial Committee of the Special Section on Test and Verification of VLSI Full Text: CiNii
Editorial Committee of the Special Section on Cellular Automata Full Text: CiNii
Special Section on Test and Verification of VLSI Full Text: CiNii	529
Generation of Test Sequences with Low Power Dissipation for Sequential Circuits(Test Generation and Compaction)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	530-536
Test Sequence Generation for Test Time Reduction of IDDQ Testing(Test Generation and Compaction)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	537-543
Don't Care Identification and Statistical Encoding for Test Data Compression(Test Generation and Compaction)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	544-550
CMOS Floating Gate Defect Detection Using Supply Current Test with DC Power Supply Superposed by AC Component(Fault Detection)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	551-556
Layout-Based Detection Technique of Line Pairs with Bridging Fault Using I_<DDQ>(Fault Detection)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	557-563
Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits(Fault Detection)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	564-570
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits(Fault Detection)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	571-579
A New Solution to Power Supply Voltage Drop Problems in Scan Testing(Scan Testing)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	580-585
Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits(Scan Testing)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	586-591
Fault Diagnosis for RAMs Using Walsh Spectrum(Memory Testing)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	592-600
Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults(Memory Testing)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	601-608
A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	609-619
Preemptive System-on-Chip Test Scheduling(SoC Testing)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	620-629
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification(Verification)(<Special Section>Test and Verification of VLSI) Full Text: CiNii	630-636
Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions(<Special Section>Test and Verification of VLSI) Full Text: CiNii	637-641
Analog Circuit Test Using Transfer Function Coefficient Estimates(<Special Section>Test and Verification of VLSI) Full Text: CiNii	642-646
Special Section on Cellular Automata Full Text: CiNii	647-649
Simple Universal Reversible Cellular Automata in Which Reversible Logic Elements Can Be Embedded(<Special Section>Cellular Automata) Full Text: CiNii	650-656
On Signals in Asynchronous Cellular Spaces(<Special Section>Cellular Automata) Full Text: CiNii	657-668
Situated Cellular Agents : A Model to Simulate Crowding Dynamics(<Special Section>Cellular Automata) Full Text: CiNii	669-676
Initialising Cellular Automata in the Hyperbolic Plane(<Special Section>Cellular Automata) Full Text: CiNii	677-686
The Fault-Tolerant Early Bird Problem(<Special Section>Cellular Automata) Full Text: CiNii	687-693
A Logically Universal Number-Conserving Cellular Automaton with a Unary Table-Lookup Function(<Special Section>Cellular Automata) Full Text: CiNii	694-699
Time and Space Complexity Classes of Hyperbolic Cellular Automata(<Special Section>Cellular Automata) Full Text: CiNii	700-707
Prefix Computations on Iterative Arrays with Sequential Input/Output Mode(<Special Section>Cellular Automata) Full Text: CiNii	708-712
Displaying Images with Cellular Automata(<Special Section>Cellular Automata) Full Text: CiNii	713-720
On the Descriptional Complexity of Iterative Arrays(<Special Section>Cellular Automata) Full Text: CiNii	721-725
Extended Floor Field CA Model for Evacuation Dynamics(<Special Section>Cellular Automata) Full Text: CiNii	726-732
A Simple Design of Time-Efficient Firing Squad Synchronization Algorithms with Fault-Tolerance(<Special Section>Cellular Automata) Full Text: CiNii	733-739
Discrete Simulation of Reactive Flow with Lattice Gas Automata(<Special Section>Cellular Automata) Full Text: CiNii	740-744
An Efficient Algorithm for Computing the Reliability of Stochastic Binary Systems(Algorithms) Full Text: CiNii	745-750
Delaying Coherence Requests to Enhance the Performance of Strict Consistency Models(Computer Systems) Full Text: CiNii	751-760
Fast Algorithms for Mining Generalized Frequent Patterns of Generalized Association Rules(Databases) Full Text: CiNii	761-770
XML Content Update Using Relative Region Coordinates(Databases) Full Text: CiNii	771-779
An Optimal Material Distribution System Based on Nested Genetic Algorithm(Algorithms) Full Text: CiNii	780-784
Medical Endoscopic Image Segmentation Using Snakes(Image Processing, Image Pattern Recognition) Full Text: CiNii	785-789
ABSTRACTS(IEICE Trans. Inf. & Syst.(Japanese Edition), Vol.J87-D-I, J87-D-II, No.3) Full Text: CiNii	790-797
Call for Papers Full Text: CiNii
Alphabetical List of Reviewers of This Year's Issues Full Text: CiNii
BACKCOVER Full Text: CiNii

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