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表紙
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目次
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On Improving Transition Fault Coverage of Stuck-at Fault Tests Using Don't Care Identification Technique
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1-6
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An Integer Programming Formulation for Generating High Quality Transition Tests
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7-12
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A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
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13-18
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Analysis of Open Faults using TEG Chip
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19-24
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Area Efficient Multipliers Utilizing the Sum of Operands
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25-30
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Hardware Algorithm for Division in GF(2^m) Based on the Extended Euclid's Algorithm Accelerated with Parallelization of Modular Reductions
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31-36
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Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit
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37-42
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A Parallel Hardware Engine for Generating Deformed Maps
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43-48
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Scan-based Attack for an AES-LSI included with other IPs
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49-53
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Dynamically Variable Secure Scan Architecture against Scan-based Side Channel Attack on Cryptography LSIs
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55-59
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A Power Masking Method of AES Circuit by Using Cross Bar Switch to Switch S-Box Circuit
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61-66
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On Handling Cell Placement With Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design
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67-72
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CAFE router: A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles
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73-78
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Coarse-Grained Reconfigurable Architecture with Flexible Reliability
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79-84
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Insertion-Point Selection of Canary FF for Timing Error Prediction
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85-89
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Evaluating the reliability of Highly Reliable Cell Circuits
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91-96
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A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems
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97-102
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Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay
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103-108
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Improving the Accuracy of Rule-based Equivalence Checking of High-level Descriptions by Identifying Potential Internal Equivalences
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109-114
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Generation of High Coverage Property Set Using Counterexamples
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115-120
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A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment
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121-126
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A Hybrid Delay Scan for Delay Testing Based on Propagation Dominance
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127-132
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A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains
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133-138
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Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations
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139-144
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A Multiplexer Reducing Algorithm in Floorplan-Aware High-level Synthesis for Distributed-Register Architectures
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145-150
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Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints
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151-156
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Enlarging The Solution Space For Schedulability Based On Skew Optimization
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157-162
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Accuracy and Speed Improvement of Random Walk Simulation Using Walk Sharing and Return-to-Start Transient Analysis Technique
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163-170
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Delay analysis method using stochastic process
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171-175
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Power Noise Analysis Acceleration Technique by Linear Programming Method
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177-182
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Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
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183-188
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複写される方へ
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Notice for Photocopying
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奥付
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