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表紙
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目次
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On the Acceleration of Threshold Test Generation Based on Fault Acceptability
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1-6
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A test pattern generation method to reduce the number of detected untestable faults on scan testing
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7-12
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On the Acceleration of Redundancy Identification for Hard-to-ATPG faults Using SAT
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13-18
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Decimal adder using abacus architecture and its application to residue arithmetic
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19-23
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History based scheduling for reliable Volunteer Computing
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25-30
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A method for generating defect oriented test patterns for combinatorial circuit
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31-36
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On Tests to Detect Open faults with Considering Adjacent Lines
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37-42
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Note on Small Delay Fault Model for Intra-Gate Resistive Open Defects
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43-48
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A Method to Increase the Number of Don't care based on Easy-To-Detected Faults : Application for BAST Architecture
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49-54
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Resource Binding to Minimize the Number of RTL Paths
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55-60
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A Secure Scan Design Approach Using Extended de Bruijn Graph
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61-66
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複写される方へ
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Notice for Photocopying
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奥付
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