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表紙
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目次
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A study of software development environment for dynamic-reconfigurable processor MuCCRA-3
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1-6
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Reducing scheduling overheads in Dynamically Reconfigurable Processors
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7-12
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Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization
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13-18
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Evaluation using Applications for RC-OS which supports Reconfigurable Computer System
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19-24
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A network deliverable hw/sw complex, video codec
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25-30
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Development of Interdisciplinary Research Environment by Collaboration of e-Learning and Remote FPGA
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31-34
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FPGA Implementation of Discrete Wavelet Transform Using Impulse C
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35-40
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An FPGA Implementation of Array Processor Performing 3D-DCT Effectively
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41-46
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Computer Aided Detection System Implementation for recognize cancer in Mammograms over an FPGA
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47-52
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A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure
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53-58
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Design of Reconfigurable Logic Device based on Variable Grain Logic Cell
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59-64
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Residue-Binary Conversion Using Signed-Digit Number Arithmetic
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71-76
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Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation
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77-82
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Hardware Specialization of Digital Filters for Vibration Control
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83-88
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A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching
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89-94
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Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control
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95-99
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Implementation of Power Reduction with Dynamically Dual-V_<DD> Assignment to Dynamically Reconfigurable Processor Array
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101-106
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Granularity Optimization Method for AES Encryption Implementation on CUDA
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107-112
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Effective Hardware Task Context Switching in Virtex-4 FPGAs
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113-118
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Hardware Acceleration in a Scalable FPGA System
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119-124
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Expansion of Hardware in a Scalable FPGA System
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125-130
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An efficient hardware-oriented algorithm for regular expression matching based on parallel bit-distribution
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131-136
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Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers
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137-142
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A Packet Classifier Using a Parallel Branching Program Machine
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143-148
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An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs
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149-154
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Fault Recovery Technique for Softcore Processor using Partial Reconfiguration
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155-160
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An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
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161-166
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A remote dynamic optically reconfigurable gate array using a fiber array
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167-170
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Compensation method for photodiode characteristics variation using an analog configuration context
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171-174
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A programmable optically reconfigurable gate array with a silver-halide holographic memory
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175-179
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複写される方へ
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奥付
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