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表紙
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目次
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A Field-Programmable Gate Array Architecture with Fault Detection and Recovery Capability
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1-8
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Two-Color Two-Rail Current-Mode Multiple-Valued Asynchronous VLSI System and Its Applications
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9-15
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Self-Checking Multiple-Valued Integrated Circuit Based on Dual-Rail Current-Mode Logic and Its Application to a High-Performance Arithmetic VLSI System
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17-24
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High-Performance Path Planning VLSI Processor and Its Application to Highly-Safe Intelligent Vehicles
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25-31
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Pattern Recognition LSI's Designed by Direct Data Implementation Technique Using an Evolutionary Algorithm
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33-40
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Self-Reconfigurations of Mesh-Connected Processor Arrays with Spares on Two Sides
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41-48
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A Fault Injection Approach for Multiple-Weight-Fault Tolerance of Multi-Layered Neural Networks
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49-56
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Fault-Tolerant Design of Mutually Coupled Neural Networks based on the Duplication of Neurons with the Higher Functionality
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57-64
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Verification of asynchronous circuits including data-paths
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65-72
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A Non-Scan Testable Design of Sequential Circuits
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73-79
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A New Data Structure for SAT-Based Static Learning with Impact on Test Generation
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81-88
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Single Byte Error Control Codes with Double Bit Within a Block Error Correcting Capability for Semiconductor Memory Systems
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89-96
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[OTHERS]
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