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表紙
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目次
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Trends and Multi-Level-Cell Technology of Spin Transfer Torque Memory
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1-5
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A Technical Trend and Embedded DRAM Technology for High-Performance NAND Flash Memories
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7-12
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ReRAM Test Macro with High Speed Read/Program Circuit : Conductive Bridge ReRAM with 2.3GB/s Read throughput and 216MB/s Program-throughput
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13-18
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A 151mm^2 64Gbit 2bit/cell NAND Flash Memory Fabricated in 24nm Technology
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19-26
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Highly reliable, high speed Solid-State Drive (SSD)
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27-32
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Trend in Phase Change Memory and activity in TIA
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33-36
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3-Dimentional NAND Flash Memories
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37-42
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0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM
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43-48
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A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
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49-54
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Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs
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55-58
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0.5-V FinFET SRAM Using Dynamic-Threshold-Voltage Pass Gates
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59-63
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0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme
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65-70
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Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor
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71-76
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A 12Gb/s Non-Contact Interface with Coupled Transmission Lines
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77-80
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1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing
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81-86
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Design of Program-voltage (20V) Booster and TSV for High Speed and Low Power 3-D Solid State Drive System
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87-92
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Basic memory characteristics of HfO_2-CB-RAM
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93-97
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Physical Analysis on ReRAM Filaments Using Atomic Force Microscope
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99-104
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Switching Mechanism of Perovskite-Oxide-Based Resistive Random Access Memory (ReRAM)
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105-109
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Analyses on Co-relation between Low and High Resistance States in ReRAM Consisting of Binary-Transition-Metal-Oxides
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111-116
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複写される方へ
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奥付
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裏表紙
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