IPSJ SIG Notes Information Processing Society of Japan (IPSJ) 2000(74) (20000803)

 CiNii Books

表紙  Full Text: CiNii   
目次  Full Text: CiNii   
2000-ARC-139-1 Evaluation of Cache Systems on Shared-Memory Multiprocessors, Using Memory-Bus Trace  Full Text: CiNii    1-6
2000-ARC-139-2 Quantitative Evaluation of Scalable Directory Schemes in Hardware Distributed Shared Memory  Full Text: CiNii    7-12
2000-ARC-139-3 Improvement of the Speculative Memory Access Mechanism:spec MEM  Full Text: CiNii    13-18
2000-ARC-139-4 Evaluation of Distributed Shared Memory System of the JUMP-1 Multiprocessor  Full Text: CiNii    19-24
2000-ARC-139-5 Reduction of Quadratic Equations for Data Dependence Tests  Full Text: CiNii    25-30
2000-ARC-139-6 Applying Dynamic Programming Technique to Register Allocation Based on Series-parallelized Register Existence Graph  Full Text: CiNii    31-36
2000-ARC-139-7 A Thread Partitioning Algorithm using Strucrural Analysis  Full Text: CiNii    37-42
2000-ARC-139-8 An Algorithm of Modulo Interval Arithmetic and Its Applications  Full Text: CiNii    43-48
2000-ARC-139-9 Very Large Data Path Architecture  Full Text: CiNii    49-54
2000-ARC-139-10 Execution Mechanism for the Very Large Data Path Architecture  Full Text: CiNii    55-60
2000-ARC-139-11 Study of Instruction Block on Very Large Data Path Architecture  Full Text: CiNii    61-66
2000-ARC-139-12 An Evaluation of A Data Preload Mechanism for A Linked List Structure  Full Text: CiNii    67-72
2000-ARC-139-13 Perfomance Evaluation of the Receiving Message Prediction Method on Different Platforms  Full Text: CiNii    73-78
2000-ARC-139-14 The Network RAID System Exploiting Mechanisms in NIC  Full Text: CiNii    79-84
2000-ARC-139-15 A parallel particle simulation machine based on EM-X and MD One  Full Text: CiNii    85-90
2000-ARC-139-16 Processor Core Architecture of Single Chip Multiprocessor for Near Fine Grain Parallel Processing  Full Text: CiNii    91-96
2000-ARC-139-17 Reducing I-Cache Miss Penalty by I-Fetch Instruction  Full Text: CiNii    97-102
2000-ARC-139-18 Instruction issue logic of the Dualflow architecture  Full Text: CiNii    103-108
2000-ARC-139-19 A low-latency instruction scheduling scheme for superscalars  Full Text: CiNii    109-114
2000-ARC-139-20 Instruction Fetch Mechanism for On-chip Multi Processor  Full Text: CiNii    115-120
2000-ARC-139-21 Scheduling Support Hardware for Multiprocessor System and its Evaluations  Full Text: CiNii    121-126
2000-ARC-139-22 Instruction fetch mechanism based on instruction behavior detection  Full Text: CiNii    127-132
2000-ARC-139-23 TaMTaM-Trace Analyzer for Multi-Threading Architecture Model  Full Text: CiNii    133-138
2000-ARC-139-24 Cogeneration of an Embeded Microprocessor and Its Object Code to Minimize Memory Consumption  Full Text: CiNii    139-144
2000-ARC-139-25 Extension of the Reconfigurable Simulation System, RiSP  Full Text: CiNii    145-150
2000-ARC-139-26 Implementation and Evaluation of a Multi-Threading Processor Based on MIPS Architecture by Using FPGA  Full Text: CiNii    151-156
2000-ARC-139-27 Preliminary Evaluation of Data Value Prediction for A Speculative Parallel Execution of Loop Iterations  Full Text: CiNii    157-162
2000-ARC-139-28 Unlimited Speculative Execution for Loops  Full Text: CiNii    163-168
2000-ARC-139-29 Java Bytecode Execution Using Data Value Reuse with Speculative Preloading  Full Text: CiNii    169-174
2000-ARC-139-30 Multi-path Speculative Execution Model with Program-counter Queues  Full Text: CiNii    175-180
2000-ARC-139-31 Dynamic Scheduling with Overlapping Assignment for Coarse-Grain Task Parallel Processing  Full Text: CiNii    181-186
2000-ARC-139-32 Coarse Grain Task Parallel Processing with OpenMP API  Full Text: CiNii    187-192
裏表紙  Full Text: CiNii