Search Results1-20 of  24

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  • 大畠 賢一 ID: 9000009243215

    Articles in CiNii:1

    • 超高速メモリ用デコ-ダの検討 (1991)
  • 大畠 賢一 ID: 9000258451071

    鹿児島大 (2004 from CiNii)

    Articles in CiNii:1

    • FBGを用いた光ファイバ防災システムのシミュレーションモデルの検討 (2004)
  • 大畠 賢一 ID: 9000314073996

    Articles in CiNii:1

    • Study on a tolerance for process variability in Single Slope ADC using interpolative TDC (2015)
  • 大畠 賢一 ID: 9000314074172

    Articles in CiNii:1

    • Study on a tolerance for process variability in Single Slope ADC using interpolative TDC (2015)
  • 大畠 賢一 ID: 9000347209542

    Articles in CiNii:1

    • Consideration on High-Output-Impedance Current Mirror for Single-Slope ADC (2014)
  • 大畠 賢一 ID: 9000347209580

    Articles in CiNii:1

    • A high-speed comparator for parallel architecture AD Converters (2014)
  • 大畠 賢一 ID: 9000397936758

    Articles in CiNii:1

    • Unit Capacitor Placement Algorithm to Suppress Capacitance Mismatch due to Erosion (2018)
  • 大畠 賢一 ID: 9000403153723

    鹿児島大 (2017 from CiNii)

    Articles in CiNii:1

    • Nonlinear factor analysis for dynamic VTC (2017)
  • 大畠 賢一 ID: 9000403153725

    鹿児島大 (2017 from CiNii)

    Articles in CiNii:1

    • Performance Comparison Between Vernier TDC and Interpolation TDC (2017)
  • OHHATA Kenichi ID: 9000018708141

    Kagoshima University (2012 from CiNii)

    Articles in CiNii:52

    • Bandwidth enhancement technique for transimpedance amplifier using negative impedance circuit (2009)
    • A 90-nm CMOS 4×10Gb/s VCSEL Driver using Asymmetric Emphasis Technique for Optical Interconnection (2009)
    • Technique for improving power supply rejection ratio in transimpedance amplifier design (2012)
  • OHHATA Kenichi ID: 9000244924816

    Dept. of Electrical and Electronics Engineering, Kagoshima University (2013 from CiNii)

    Articles in CiNii:4

    • 1-GHz, 8-bit Subranging ADC(1) : Low-power techniques (2013)
    • 1-GHz, 8-bit Subranging ADC(2) : Experimental results and failure analysis (2013)
    • Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC (2013)
  • OHHATA Kenichi ID: 9000262058016

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-8 Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC (2014)
  • OHHATA Kenichi ID: 9000262058136

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-41 Power Reduction Technique for Clock Bootstrap Circuit (2014)
  • OHHATA Kenichi ID: 9000280546520

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-13 Design of 300-MS/s, 8-bit, Two-Step Single Slope ADC (2014)
  • OHHATA Kenichi ID: 9000280546522

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-14 Low Energy Comparator Using Temporal Boost Technique (2014)
  • OHHATA Kenichi ID: 9000301386621

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2015 from CiNii)

    Articles in CiNii:1

    • C-12-32 A 0.5-V, 1.2-GHz, 6-bit Flash ADC Using Temporal-Boost Comparator (2015)
  • Ohhata K. ID: 9000004746683

    Musashino Office, Hitachi Device Engineering Co., Ltd. (2008 from CiNii)

    Articles in CiNii:28

    • A 43-Gb/s Low-jitter Output-circuit Design for a 16 : 1 MUX IC Module Based on SiGe HBT Technology (2003)
    • A 43-Gb/s Low-jitter Output-circuit Design for a 16:1 MUX IC Module Based on SiGe HBT Technology (2003)
    • IC Modules for 40-Gb/s Optical Transmission Systems Using SiGe-HBTs (2002)
  • Ohhata Kenichi ID: 9000045921331

    Kagoshima University (2005 from CiNii)

    Articles in CiNii:1

    • B-13-21 An Investigation of method of connecting Sensor in Fiber-Optic Disaster Prevention System using FBGs (2005)
  • Ohhata Kenichi ID: 9000242894183

    Dept. of Electrical and Electronics Engineering, Kagoshima University (2013 from CiNii)

    Articles in CiNii:1

    • Comparator Topology Suited for Low-Voltage Operation (2013)
  • Ohhata Kenichi ID: 9000258452574

    Kagoshima University (2005 from CiNii)

    Articles in CiNii:1

    • An Investigation of Fiber-Optic Disaster Prevention System simulator using FBGs (2005)
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