Search Results1-20 of  192

  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000046011481

    Faculty of Science and Technology, Keio University:National Institute of Informatics (2015 from CiNii)

    Articles in CiNii:22

    • Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs (2011)
    • A good similarity of a datapath classification method for FPGA-based accelerator systems (2011)
    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • AMANO Hideharu ID: 9000259594727

    慶應義塾大学理工学部|国立情報学研究所 (2015 from CiNii)

    Articles in CiNii:19

    • A configurable switch mechanism for random NoCs (2014)
    • A Case for Low-Power Networks using FSO and On/Off Links (2014)
    • Implementation of MuCCRA-4 : Dynamically Reconfigurable Processor Array (2014)
  • AMANO Hideharu ID: 9000259594727

    慶應義塾大学理工学部|国立情報学研究所 (2015 from CiNii)

    Articles in CiNii:19

    • A configurable switch mechanism for random NoCs (2014)
    • A Case for Low-Power Networks using FSO and On/Off Links (2014)
    • Implementation of MuCCRA-4 : Dynamically Reconfigurable Processor Array (2014)
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