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  • YAMASHITA Takeo ID: 9000004753299

    Department of Electronic Engineering, Tohoku University (1995 from CiNii)

    Articles in CiNii:3

    • Neuron-MOS Multiple-Valued Intelligent Memory Technology (1994)
    • A Neuron-MOS Data Sorting Circuit (1995)
    • Neuron MOS Winner-Take-All Circuit and Its Application to Associative Memory (1993)
  • YAMASHITA Takeo ID: 9000004781201

    Device Development Center, Hitachi Ltd., Tokyo, Japan (2001 from CiNii)

    Articles in CiNii:5

    • A 450MHz 64bit RISC Processor using Multiple Threshold Voltage CMOS (2000)
    • A 450MHz 64bit RISC Processor using Multiple Threshold Voltage CMOS (2000)
    • Design Methodology of High Performance Microprocessor using Ultra-Low Threshold Voltage CMOS (2001)
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