Search Results1-20 of  196

  • 戸川 望 ID: 9000010404382

    Articles in CiNii:1

    • 組み込みシステム解剖室(新連載・第1回)ディジタル一眼レフ・カメラを解剖する (2007)
  • 戸川 望 ID: 9000241627608

    Articles in CiNii:1

    • A Time and Area Constraint-based Fault-Secure High-Level Synthesis Algorithm for RDR Architectures (2013)
  • 戸川 望 ID: 9000241627637

    Articles in CiNii:1

    • Scan-based Attack against Trivium Stream Cipher Independent of Scan Structure (2013)
  • 戸川 望 ID: 9000241628995

    Articles in CiNii:1

    • Scan-based Attack for Block Ciphers Using Scan Signatures (2013)
  • 戸川 望 ID: 9000241843643

    Articles in CiNii:1

    • A Bi-Linear Interpolation Unit Using Selector Logics (2013)
  • 戸川 望 ID: 9000241843657

    Articles in CiNii:1

    • Scan-based Attack on the LED Block Cipher Using Scan Signatures (2013)
  • 戸川 望 ID: 9000241843729

    Articles in CiNii:1

    • A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations (2013)
  • 戸川 望 ID: 9000241873344

    Articles in CiNii:1

    • High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation (2010)
  • 戸川 望 ID: 9000242793220

    Presently with Dept. of Computer Science and Engineering, Waseda University (2013 from CiNii)

    Articles in CiNii:1

    • フロアプランを考慮したマルチクロックドメイン指向の低電力化高位合成手法(動作合成,組込み技術とネットワークに関するワークショップETNET2013) (2013)
  • 戸川 望 ID: 9000259295838

    Articles in CiNii:1

    • An Interconnect-Delay-Aware High-Level Synthesis Algorithm with Operation Chainings Using Chaining Enumeration (2014)
  • 戸川 望 ID: 9000279915177

    早稲田大学大学院基幹理工学研究科情報理工学専攻 (2015 from CiNii)

    Articles in CiNii:1

    • Improved scan-based side-channel attack on the LED block cipher (2015)
  • 戸川 望 ID: 9000279915422

    早稲田大学大学院基幹理工学研究科情報理工学専攻 (2015 from CiNii)

    Articles in CiNii:1

    • Improved scan-based side-channel attack on the LED block cipher (2015)
  • 戸川 望 ID: 9000286639320

    早稲田大学大学院基幹理工学研究科 (2015 from CiNii)

    Articles in CiNii:1

    • AES Encryption Circuit against Clock Glitch based Fault Analysis (2015)
  • 戸川 望 ID: 9000286971943

    Articles in CiNii:1

    • Layout CAD Methods for FPAGAs (1994)
  • 戸川 望 ID: 9000287200166

    Articles in CiNii:1

    • A Task Mapping Algorithm for Network-based Multi-FPGA Systems (2014)
  • 戸川 望 ID: 9000287200187

    Articles in CiNii:1

    • A High-Level Synthesis Algorithm with Delay Variation Tolerance Adjustment for RDR Architectures (2014)
  • 戸川 望 ID: 9000287200191

    Articles in CiNii:1

    • An Effective Robust Design for Large Delay Variation Using Suspicious Timing-Error Prediction Scheme (2014)
  • 戸川 望 ID: 9000287200217

    Articles in CiNii:1

    • A foorplan-driven FPGA high-level synthesis algorithm for multiplexer reduction (2014)
  • 戸川 望 ID: 9000287200220

    Articles in CiNii:1

    • An Interconnection-Delay-Aware High-Level Synthesis Algorithm with Multiple-Operation Chainings (2014)
  • 戸川 望 ID: 9000287200249

    Articles in CiNii:1

    • A Bi-Linear Interpolation Circuit Using 4-to-1 and 2-to-1 Selector Logics and Its Evaluations (2014)
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