Search Results1-16 of  16

  • 木村 晋二 ID: 9000010490783

    Articles in CiNii:1

    • Optimal planer jumping systolic array design for matrix multiplication (第20回 回路とシステム軽井沢ワークショップ論文集) -- (演算器設計) (2007)
  • 木村 晋二 ID: 9000019109906

    Articles in CiNii:1

    • SEU correctable AES circuits based on Hamming Code (2012)
  • 木村 晋二 ID: 9000286972198

    Articles in CiNii:1

    • Parallel Binary Decision Diagram Manipulation (1993)
  • 木村 晋二 ID: 9000377384881

    Articles in CiNii:1

    • Implementation and Optimization of Parallel Prefix Adders Using Majority Function (2017)
  • 木村 晋二 ID: 9000377386335

    Articles in CiNii:1

    • Implementation and Optimization of Parallel Prefix Adders Using Majority Function (2017)
  • 木村 晋二 ID: 9000403556999

    Articles in CiNii:1

    • Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters (2009)
  • 木村 晋二 ID: 9000404086232

    Articles in CiNii:1

    • Data Structure for Quantum Annealing Emulator (2019)
  • 木村 晋二 ID: 9000404292724

    Articles in CiNii:1

    • Automatic Insertion of Forward Sequential Clock Gating Logic Using Time Expanded Circuits (2016)
  • KIMURA SHINJI ID: 9000004348696

    Articles in CiNii:8

    • 論理回路の入力制約および入出力仕様の記述とその検証 (1986)
    • 時相論理に対応する形式言語 (1987)
    • 新しい連接による拡張正規表現について (1987)
  • KIMURA Shinji ID: 1000020183303

    Articles in CiNii:180

    • Examination of Animation System of Sign Language Words Available from Web (2002)
    • Space Allocation Method Based on Architectural View from Conversational Requirement (2002)
    • Efficient Hardware Architecture of a New Simple Public-Key Cryptosystem for Real-Time Data Processing (2005)
  • KIMURA Shinji ID: 9000241128382

    Graduate School of Fundamental Science and Engineering, Waseda University (2012 from CiNii)

    Articles in CiNii:5

    • Write Reduction for Non-volatile Registers Using the Max-flow Min-cut (2012)
    • Write Reduction for Non-volatile Registers Using the Max-flow Min-cut (2012)
    • Write Reduction for Non-volatile Registers Using the Max-flow Min-cut (2012)
  • KIMURA Shinji ID: 9000282785388

    Graduate School of Fundamental Science and Engineering, Waseda University (2013 from CiNii)

    Articles in CiNii:1

    • Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers (2013)
  • KIMURA Shinji ID: 9000285078935

    Graduate School of Fundamental Science and Engineering, Waseda University (2013 from CiNii)

    Articles in CiNii:1

    • Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers (2013)
  • KIMURA Shinji ID: 9000391780393

    Waseda university (2002 from CiNii)

    Articles in CiNii:1

    • Dynamic Updating and Linking of Active Software (2002)
  • Kimura Shinji ID: 9000258450543

    早大 (2004 from CiNii)

    Articles in CiNii:1

    • Skin color detection based user interface development (2004)
  • Kimura Shinji ID: 9000283832565

    早大 (2010 from CiNii)

    Articles in CiNii:1

    • Pseudo Power Gating Method Based on the Controlling Values of Logic Gates (2010)
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