Search Results1-20 of  133

  • 柳澤 政生 ID: 9000241627619

    Articles in CiNii:1

    • Random Order Scan Design against Scan-Based Attacks (2013)
  • 柳澤 政生 ID: 9000259296086

    Articles in CiNii:1

    • A Network-flow-based Checkpoint Insertion Algorithm for Suspicious Timing Error Prediction Scheme (2014)
  • 柳澤 政生 ID: 9000259296146

    Articles in CiNii:1

    • A non-volatile memory writing method based on state encoding limiting maximum and minimum Hamming distances (2014)
  • 柳澤 政生 ID: 9000286639310

    早稲田大学大学院基幹理工学研究科電子物理システム学専攻 (2015 from CiNii)

    Articles in CiNii:1

    • Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits (2015)
  • 柳澤 政生 ID: 9000287200186

    Articles in CiNii:1

    • A High-Level Synthesis Algorithm with Delay Variation Tolerance Adjustment for RDR Architectures (2014)
  • 柳澤 政生 ID: 9000287200190

    Articles in CiNii:1

    • An Effective Robust Design for Large Delay Variation Using Suspicious Timing-Error Prediction Scheme (2014)
  • 柳澤 政生 ID: 9000287200216

    Articles in CiNii:1

    • A foorplan-driven FPGA high-level synthesis algorithm for multiplexer reduction (2014)
  • 柳澤 政生 ID: 9000287200219

    Articles in CiNii:1

    • An Interconnection-Delay-Aware High-Level Synthesis Algorithm with Multiple-Operation Chainings (2014)
  • 柳澤 政生 ID: 9000287200248

    Articles in CiNii:1

    • A Bi-Linear Interpolation Circuit Using 4-to-1 and 2-to-1 Selector Logics and Its Evaluations (2014)
  • 柳澤 政生 ID: 9000287200251

    Articles in CiNii:1

    • FPGA Implementation and Evaluation of Image Scaling Circuits Using Seletor-Logic-Based Bi-Linear Interpolation (2014)
  • 柳澤 政生 ID: 9000287207572

    Articles in CiNii:1

    • A Curved Road-network Shaping Algorithm for Smoothly-connected Deformed Map Generation (2014)
  • 柳澤 政生 ID: 9000287207589

    Articles in CiNii:1

    • An Indoor Pedestrain Navigation System based on Visibility Graphs Considering Walking Passage Shapes (2014)
  • 柳澤 政生 ID: 9000287207595

    Articles in CiNii:1

    • An Outdoor Pestrian Navigation System Using Visible Landmarks (2014)
  • 柳澤 政生 ID: 9000296676374

    Articles in CiNii:1

    • Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits (2015)
  • 柳澤 政生 ID: 9000314074456

    Articles in CiNii:1

    • A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs (2015)
  • 柳澤 政生 ID: 9000314074713

    Articles in CiNii:1

    • Hardware Trojan Identification based on Netlist Features using SVM (2015)
  • 柳澤 政生 ID: 9000314076285

    Articles in CiNii:1

    • A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories (2015)
  • 柳澤 政生 ID: 9000314076847

    Articles in CiNii:1

    • A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs (2015)
  • 柳澤 政生 ID: 9000314077023

    Articles in CiNii:1

    • Hardware Trojan Identification based on Netlist Features using SVM (2015)
  • 柳澤 政生 ID: 9000314077344

    Articles in CiNii:1

    • A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories (2015)
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