Search Results1-20 of  26

  • 1 / 2
  • 梶原 誠司 ID: 9000010490778

    Articles in CiNii:1

    • High quality delay testing for logic circuits (2007)
  • 梶原 誠司 ID: 9000343340943

    Articles in CiNii:1

    • 特別講演 VLSIテスト技術によるシステムディペンダビリティ向上への期待 (2016)
  • 梶原 誠司 ID: 9000356548906

    Articles in CiNii:1

    • IR-Drop Analysis on Different Power Supply Network Designs (2017)
  • 梶原 誠司 ID: 9000362203681

    Articles in CiNii:1

    • Feasibility Evaluation of the Statistical Delay Quality Model (SDQM) (2006)
  • 梶原 誠司 ID: 9000363903772

    Articles in CiNii:1

    • A Two-Temperature-Point Calibration Method for A Digital Temperature And Voltage Sensor (2017)
  • 梶原 誠司 ID: 9000377384793

    Articles in CiNii:1

    • Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST (2017)
  • 梶原 誠司 ID: 9000377386276

    Articles in CiNii:1

    • Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST (2017)
  • 梶原 誠司 ID: 9000380485553

    Articles in CiNii:1

    • A Test Clock Observation Method Using Time-to-Digital Converters for Built-in Self-Test in FPGAs (2017)
  • 梶原 誠司 ID: 9000388461829

    Articles in CiNii:1

    • Locating Hot Spot with Justification Techniques in a Layout Design (2018)
  • 梶原 誠司 ID: 9000388462284

    Articles in CiNii:1

    • A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor (2018)
  • 梶原 誠司 ID: 9000399575864

    Articles in CiNii:1

    • Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips (2018)
  • 梶原 誠司 ID: 9000404221369

    Articles in CiNii:1

    • A Fully-digital Temperature Monitor Using Ring Oscillator on FPGA (2015)
  • 梶原 誠司 ID: 9000404239032

    Articles in CiNii:1

    • LC-3 テストパターン中の特定ビットにおけるドントケア判定法について(C. アーキテクチャ・ハードウェア) (2002)
  • 梶原 誠司 ID: 9000404292685

    Articles in CiNii:1

    • A Flexible Scan-in Power Control Method for Scan-Based Logic BIST and Its Evaluation on TEG Chips (2016)
  • KAJIHARA Seiji ID: 1000080252592

    Computer Science and Systems Engineering, Kyushu Institute of Technology (2014 from CiNii)

    Articles in CiNii:175

    • Removal of Redundancy in Combinational Circuits by Classification of Undetectable Faults (1992)
    • On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume (2003)
    • Multiple Scan Tree Design for Test Compression (2003)
  • KAJIHARA Seiji ID: 9000004743436

    Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology:Center for Microelectronics Systems, Kyushu Institute of Technology (2003 from CiNii)

    Articles in CiNii:1

    • Estimation of Fault Coverage in Path Delay Fault Testing (2003)
  • KAJIHARA Seiji ID: 9000107314868

    Kyushu Institute of Technology (2011 from CiNii)

    Articles in CiNii:1

    • Capture Power Reduction in Multi-cycle Test Structure (2011)
  • KAJIHARA Seiji ID: 9000107317976

    Kyushu Institute of Technology (2011 from CiNii)

    Articles in CiNii:1

    • Capture Power Reduction in Multi-cycle Test Structure (2011)
  • KAJIHARA Seiji ID: 9000107319987

    Kyushu Institute of Technology (2012 from CiNii)

    Articles in CiNii:1

    • Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test (2012)
  • KAJIHARA Seiji ID: 9000107321758

    Kyushu Institute of Technology (2008 from CiNii)

    Articles in CiNii:1

    • Transistor Aging and Operational Environment of Logic Circuits (2008)
  • 1 / 2
Page Top