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  • 金子 峰雄 ID: 9000008213983

    Articles in CiNii:5

    • Switched-Capacitor回路の等価表現とその応用 (1982)
    • スイッチトキャパシタ回路の位相幾何学的性質 (1983)
    • 状態差分方程式表現に基づく浮遊容量不感スイッチトキャパシタ回路の構成 (1987)
  • 金子 峰雄 ID: 9000019120607

    Articles in CiNii:2

    • Energy Stability-aware Scheme for Intelligent Home Energy Management System (2012)
    • Energy Stability-aware Scheme for Intelligent Home Energy Management System (2012)
  • 金子 峰雄 ID: 9000242256315

    Articles in CiNii:1

    • Adjacent Insertion and Its Effectiveness in Code-Based 3-D Placement (2010)
  • 金子 峰雄 ID: 9000242256590

    Articles in CiNii:1

    • ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding (システムLSI設計技術(SLDM) Vol.2010-SLDM-147) (2010)
  • 金子 峰雄 ID: 9000388460674

    Articles in CiNii:1

    • Congestion Aware High Level Synthesis Design Flow with Source Compiler (2018)
  • 金子 峰雄 ID: 9000388460904

    Articles in CiNii:1

    • Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults (2018)
  • 金子 峰雄 ID: 9000388460988

    Articles in CiNii:1

    • Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths (2018)
  • 金子 峰雄 ID: 9000388461605

    Articles in CiNii:1

    • Design Optimum of Parallel Prefix Adder Considering Buffer Insertion (2018)
  • 金子 峰雄 ID: 9000401510067

    Articles in CiNii:1

    • Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis (2019)
  • 金子 峰雄 ID: 9000401510328

    Articles in CiNii:1

    • Timing Correction by Constrained Temperature Dependent Clock Skew (VLSI設計技術) (2019)
  • 金子 峰雄 ID: 9000401511578

    Articles in CiNii:1

    • Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis (2019)
  • 金子 峰雄 ID: 9000401511616

    Articles in CiNii:1

    • Timing Correction by Constrained Temperature Dependent Clock Skew (ハードウェアセキュリティ) (2019)
  • 金子 峰雄 ID: 9000404086290

    Articles in CiNii:1

    • Procedural Construction of Parallel Prefix Adder by Insertion Operation (2019)
  • 金子 峰雄 ID: 9000404292732

    Articles in CiNii:1

    • A Study on Multi-Level DVFS for Heterogeneous Task Set (2016)
  • 金子 峰雄 ID: 9000404300617

    Articles in CiNii:1

    • High Level Synthesis Design Flow with Source Compiler based on LLVM (2017)
  • 金子 峰雄 ID: 9000404307975

    Articles in CiNii:1

    • Procedural Construction of Parallel Prefix Adder (2018)
  • 金子 峰雄 ID: 9000405849330

    Articles in CiNii:1

    • Optimization of Parallel Prefix Adder Structure Generated by Insertion Operations (2019)
  • 金子 峰雄 ID: 9000405850550

    Articles in CiNii:1

    • Optimization of Parallel Prefix Adder Structure Generated by Insertion Operations (2019)
  • KANEKO Mineo ID: 1000000185935

    Articles in CiNii:172

    • Control Signal Skew Scheduling for RT Level Datapaths (2005)
    • A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning (2011)
    • The Width Constrained Placement by the Simulated Annealing with the Sequence-Pair Encoding (2002)
  • KANEKO Mineo ID: 9000107319172

    Graduate School of Information Science, Japan Advanced Institute of Science and Technology (2011 from CiNii)

    Articles in CiNii:1

    • A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning (2011)
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